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I want to write a simple backend-specific instrinsic that will just call an instruction. How should I do that? -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180924/7faeeb3d/attachment.html>

Hi all, I want to generate an assembly instruction for my target using target description representation of the instruction. The problem is that I want to add direct register to be chose as an output register for my target. Does it possible to do with an instruction definition in TARGETInstrInfo.td file? May be someone could help with an example? Currently I have seen that we can pass the name

...pecific register. > If yes, you can achieve this by creating a specialized singleton register class with the register you want and use it in the td file. > E.g., in yourTargetRegisterInfo.td: > def MyReg : RegisterClass<“MyTarget”, [Related Types], MySize, (add MyReg)>; > > in yourTargetInstrInfo.td: > def MyInstr […] (outs MyReg:$Rd) […] > > The ARM target does something similar for SP. Look for GPRsp. > If you use this approach, you may run into issues if the scheduler decides to put two instructions that write to this register class in a row. In this case you will either...