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...me as a register? If there is, I'd rather we just implement it and leave it at that. > > We can probably fix the 'flags' case easily in LLVM, but I'd rather not bend over backwards to make ZMM0 be a global name when AVX is disabled. > > On Thu, Jul 23, 2015 at 9:12 AM, Yatsina, Marina <marina.yatsina at intel.com <mailto:marina.yatsina at intel.com>> wrote: > Microsoft assembler treats mov to EAX as a register, even if there is a global memory also named EAX – meaning the register takes precedence. > > But here I have a bit of a different situation...

...plicit register or a register that does not exist in the current arch, just in future ones. Microsoft assembler treats these cases as memory locations, llvm treats them as registers, causing compilation errors. From: Reid Kleckner [mailto:rnk at google.com] Sent: Thursday, July 23, 2015 18:54 To: Yatsina, Marina Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] Intel asm syntax and variable names Suppose I have a global variable named 'EAX'. How do Intel assemblers normally escape register names to access such a global variable? On Thu, Jul 23, 2015 at 1:42 AM, Yatsina, Marina <marina....

...bol with the same name as a register? If there is, I'd rather we just implement it and leave it at that. We can probably fix the 'flags' case easily in LLVM, but I'd rather not bend over backwards to make ZMM0 be a global name when AVX is disabled. On Thu, Jul 23, 2015 at 9:12 AM, Yatsina, Marina <marina.yatsina at intel.com> wrote: > Microsoft assembler treats mov to EAX as a register, even if there is a > global memory also named EAX – meaning the register takes precedence. > > But here I have a bit of a different situation – I have a global variable, > whic...

...inline assembly. If you prefer to separate the IR changes for “asm goto” and the IR changes that will allow exposing defined symbols, then we can focus on the “asm goto” feature alone. Thanks, Marina From: Chandler Carruth [mailto:chandlerc at gmail.com] Sent: Thursday, March 30, 2017 11:21 To: Yatsina, Marina <marina.yatsina at intel.com>; llvm-dev at lists.llvm.org; rnk at google.com; jyknight at google.com; ehsan at mozilla.com; rjmccall at apple.com; mehdi.amini at apple.com; chandlerc at gmail.com; matze at braunis.de Subject: Re: [llvm-dev] [inline-asm][asm-goto] Supporting "asm...

...ng the indirecbr instruction infrastructure). We do need to make sure MachineBlockPlacement optimizes the fall through path to make sure we can gain the performance for the nop patching. Thanks, Marina From: Chandler Carruth [mailto:chandlerc at gmail.com] Sent: Thursday, March 30, 2017 23:22 To: Yatsina, Marina <marina.yatsina at intel.com>; llvm-dev at lists.llvm.org; rnk at google.com; jyknight at google.com; ehsan at mozilla.com; rjmccall at apple.com; mehdi.amini at apple.com; matze at braunis.de; Tayree, Coby <coby.tayree at intel.com> Subject: Re: [llvm-dev] [inline-asm][asm-goto...

On Tue, Apr 4, 2017 at 6:07 AM Yatsina, Marina via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Asm goto feature was introduces to GCC in order to optimize the support > for tracepoints in Linux kernel (it can be used for other things that do > nop patching). > > > > GCC documentation describes their motiv...

Suppose I have a global variable named 'EAX'. How do Intel assemblers normally escape register names to access such a global variable? On Thu, Jul 23, 2015 at 1:42 AM, Yatsina, Marina <marina.yatsina at intel.com> wrote: > Hi all, > > > > I’ve encountered an issue with x86 Intel asm syntax when using certain > variable names. > > > > If you look at the following example, where I try to do a mov to a memory > location named “flags2...

...bly usage and is enabled by default... - I still think inline assembly is valuable for new architecture bringup/experimentation situations. - Matthias > On Apr 4, 2017, at 9:26 AM, Chandler Carruth via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > On Tue, Apr 4, 2017 at 6:07 AM Yatsina, Marina via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: > Asm goto feature was introduces to GCC in order to optimize the support for tracepoints in Linux kernel (it can be used for other things that do nop patching). > > > > GCC d...

Hi all, I've encountered an issue with x86 Intel asm syntax when using certain variable names. If you look at the following example, where I try to do a mov to a memory location named "flags2", llvm- mc works fine: >cat test_good.s mov eax, flags2 >llvm-mc.exe -x86-asm-syntax=intel test_good.s -o - .text movl flags2, %eax But if the memory location is

Hi, I wanted to revive this issue of supporting asm goto (Bug 9295<https://bugs.llvm.org/show_bug.cgi?id=9295>). As was already proposed, the best way seems to be introducing new IR. If we're changing the IR, we should probably provide an infrastructure that solves or at least enables future support for things like: 1. MS-style inline asm jmps and goto (Bug

> On Feb 4, 2018, at 9:15 AM, Yatsina, Marina via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi, > > What is the best way to model a scheduler for a VLIW in-order architecture? > I’ve looked at the Hexagon and R600 architectures and they are using itineraries. I wanted to understand the benefit in using it...

Hi, What is the best way to model a scheduler for a VLIW in-order architecture? I've looked at the Hexagon and R600 architectures and they are using itineraries. I wanted to understand the benefit in using itineraries over the per operand scheduling. I also found this thread from almost 2 years ago: http://lists.llvm.org/pipermail/llvm-dev/2016-April/098763.html At that time it seemed the

...Process Explorer to discover, that the call was to ntdll.dll, which in Win8 is loaded to the totally different address. Best regards, Victor Milovanov Moscow State University graduate student 2012/3/3 Rotem, Nadav <nadav.rotem at intel.com>: > Hi Victor, > > Try this fix by Marina Yatsina: > > http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20120220/137532.html > > Nadav > > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of lost > Sent: Friday, March 02, 2012 22:53 > To: NAKAM...

Hi Krzysztof, 2018-02-08 13:32 GMT+08:00 Andrew Trick via llvm-dev < llvm-dev at lists.llvm.org>: > > > On Feb 4, 2018, at 9:15 AM, Yatsina, Marina via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > Hi, > > What is the best way to model a scheduler for a VLIW in-order architecture? > I’ve looked at the Hexagon and R600 architectures and they are using > itineraries. I wanted to understand the benefit in...

Hi Victor, Try this fix by Marina Yatsina: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20120220/137532.html Nadav -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of lost Sent: Friday, March 02, 2012 22:53 To: NAKAMURA Takumi; LLVM Subject: Re: [LLVMdev] Ac...

...ch changes the code that generates a call to '_chkstk' from PCREL32 (which uses a 32bit offset) to an indirect call (which uses a 64bit address from a register). -----Original Message----- From: lost [mailto:lostfreeman at gmail.com] Sent: Saturday, March 03, 2012 01:32 To: Rotem, Nadav; Yatsina, Marina; LLVM Subject: Re: [LLVMdev] Access Violation using ExecutionEngine on 64-bit Windows 8 Consumer Preview Hi Rotem, Thank to you, and especially to Marina! The problem gone. I'm a bit interested, what is the reason it worked in Win7, and not in Win8. I've recently used Process Expl...

Hi, Takumi! I tried your patch, and it did not help. Moreover, I tried to compile under Windows 7 and copy files to Windows 8, and received the same exception. So the problem seems to be in Windows 8 itself or some non-portable code inside LLVM. Could anyone tell me what LLVM code in ExecutionEngine is responsible for allocating and protecting memory for generated native functions? Best

...y that nothing else would. -Krzysztof On 2/8/2018 8:49 AM, 陳韋任 wrote: > Hi Krzysztof, > > 2018-02-08 13:32 GMT+08:00 Andrew Trick via llvm-dev > <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>>: > > > >> On Feb 4, 2018, at 9:15 AM, Yatsina, Marina via llvm-dev >> <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >> >> Hi,____ >> __ __ >> What is the best way to model a scheduler for a VLIW in-order >> architecture?____ >> I’ve looked a...

On Tue, 2017-04-04 at 16:26 +0000, Chandler Carruth via llvm-dev wrote: > On Tue, Apr 4, 2017 at 6:07 AM Yatsina, Marina via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Asm goto feature was introduces to GCC in order to optimize the > > support for tracepoints in Linux kernel (it can be used for other > > things that do nop patching). > >   > > GCC documentation descri...

enableAdvancedRASplitCost() does the same thing as ConsiderLocalIntervalCost, but as a subtarget option instead of a command-line option, and as I’ve said it doesn’t help because it’s a non-local interval causing the eviction chain (RAGreedy::splitCanCauseEvictionChain only considers the local interval for a single block, and it’s unclear to me how to make it handle a non-local interval). John