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2015 Jan 31
3
[LLVMdev] Encoding instructions with inconsistent formats
I'm attempting to implement codegen support for the AVR ST/LD
<http://www.atmel.com/webdoc/avrassembler/avrassembler.wb_ST.html> family
of instructions.
The binary encoding is not particularly consistent -- take a look at this
table of variants of LD, along with their machine code representation:
# load 8 bits from pointer register X into general purpose Rd
ld Rd, X `1001 000d dddd
2015 Jan 31
0
[LLVMdev] Encoding instructions with inconsistent formats
...e register is encoded. You could probably create a new
>> Operand subclass with a custom EncoderMethod that gets assigned to
>> both the dddd and the odd field.
>>
>> Something like:
>>
>> def BasicMemXYZ : Operand<i16> {
>> let MIOperandInfo = (ops XYZReg); // Sorry, don't know what you've
>> called it
>> let CustomEncoder = "encodeXYZForBasicMem";
>> }
>>
>> Associate that operand with 5 bits in the instruction instead of 4 and
>> let the C++ set the final bit as appropriate.
>>
>>...