search for: xyzgeninstrinfo

...is both modifying the DAG > and then reporting failure to select. The key questions Josh needs to > look into are: > > + Is this node there in -view-isel-dags (i.e. before selection)? > + If not, what creates it (this'll probably involve looking at > build/lib/Target/XYZ/XYZGenInstrInfo.inc to work out what 284 is. > > Calls are pretty special at the best of times, but I can't think of a > way they could cause this. > > Tim. -- Have a great day! PreeJackie

Dumb question about llvm-tblgen for "XyzGenInstrInfo.inc" If I have a pattern in my dot-td-file like this [(set i32:$dst (add i32:$rs1, i32:$rs2))] The question is where does the token "i32" come from, I don't see any definitions for i1, i8, i16, i32, ... in include/llvm/Target/*.td while I d...

Hi, Could you please explain how you are using this? like commands When I run this IR in opt, it doesn't throw any errors. On 03/03/19 1:30 AM, via llvm-dev wrote: > Hi, > > I'm having an error I've never seen before > > LLVM ERROR: Cannot select: t20: ch,glue = <<Unknown Target Node #284>> t11, TargetGlobalAddress:i32<i32 (i32, i32)* @add2> 0,

Respected Dr. Criswell, My problem is that the output of following code looks nothing like any opcode: *for(MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); ) { MachineInstr *mi = I; int op = mi->getOpcode(); std::cout << op << '\t'; }* I need to identify specific instructions in my MachineFunctionPass and I was hoping that I can

...{ return Imm >= -256 && Imm < 256; }]> { let ParserMatchClass = SImm9Operand; } Wouldn’t that work for you? Cheers, -Quentin > On May 25, 2016, at 5:06 PM, Lawrence, Peter via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Dumb question about llvm-tblgen for “XyzGenInstrInfo.inc” > > If I have a pattern in my dot-td-file like this > > [(set i32:$dst (add i32:$rs1, i32:$rs2))] > > The question is where does the token “i32” come from, > I don’t see any definitions for i1, i8, i16, i32, … in > include/llvm/...

...p;& Imm < 256; }]> { let ParserMatchClass = SImm9Operand; } Wouldn’t that work for you? Cheers, -Quentin On May 25, 2016, at 5:06 PM, Lawrence, Peter via llvm-dev <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote: Dumb question about llvm-tblgen for “XyzGenInstrInfo.inc” If I have a pattern in my dot-td-file like this [(set i32:$dst (add i32:$rs1, i32:$rs2))] The question is where does the token “i32” come from, I don’t see any definitions for i1, i8, i16, i32, … in include/llvm/Target/*.td while I do see definitions for...

...m9Operand; > } > > Wouldn’t that work for you? > > Cheers, > -Quentin > > > On May 25, 2016, at 5:06 PM, Lawrence, Peter via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: > > Dumb question about llvm-tblgen for “XyzGenInstrInfo.inc” > > If I have a pattern in my dot-td-file like this > > [(set i32:$dst (add i32:$rs1, i32:$rs2))] > > The question is where does the token “i32” come from, > I don’t see any definitions for i1, i8, i16, i32, … in > include/llvm/...

...; }]> { > let ParserMatchClass = SImm9Operand; > } > > Wouldn’t that work for you? > > Cheers, > -Quentin > > > On May 25, 2016, at 5:06 PM, Lawrence, Peter via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > Dumb question about llvm-tblgen for “XyzGenInstrInfo.inc” > > If I have a pattern in my dot-td-file like this > > [(set i32:$dst (add i32:$rs1, i32:$rs2))] > > The question is where does the token “i32” come from, > I don’t see any definitions for i1, i8, i16, i32, … in > include/llvm/Target...

...mp;& Imm < 256; }]> { let ParserMatchClass = SImm9Operand; } Wouldn’t that work for you? Cheers, -Quentin On May 25, 2016, at 5:06 PM, Lawrence, Peter via llvm-dev <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote: Dumb question about llvm-tblgen for “XyzGenInstrInfo.inc” If I have a pattern in my dot-td-file like this [(set i32:$dst (add i32:$rs1, i32:$rs2))] The question is where does the token “i32” come from, I don’t see any definitions for i1, i8, i16, i32, … in include/llvm/Target/*.td while I do see definitions for...

..., Oct 2, 2014 at 8:16 PM, Tim Northover <t.p.northover at gmail.com> wrote: > Hi Sachin, > > > int op = mi->getOpcode(); > > This is a target-specific opcode, and corresponds to one of the values > defined in (from a CMake build directory) > lib/Target/XYZ/XYZGenInstrInfo.inc. > > The easiest way to find out which is actually to use > MachineInstr::dump (and/or "llc -debug" from the command-line to print > it out automatically); if it prints something like (to pick a > completely random example from AArch64): > > %X1<def> = LDRX...

...9Operand; > > } > > > > Wouldn’t that work for you? > > > > Cheers, > > -Quentin > > > > On May 25, 2016, at 5:06 PM, Lawrence, Peter via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > > Dumb question about llvm-tblgen for “XyzGenInstrInfo.inc” > > > > If I have a pattern in my dot-td-file like this > > > > [(set i32:$dst (add i32:$rs1, i32:$rs2))] > > > > The question is where does the token “i32” come from, > > I don’t see any definitions for i1, i8, i16, i32, … in >...

in llvm-3.6.2.src 1. when I put this around one of my instruction definitions in my target "InstrInfo.td" file, let TwoOperandAliasConstraint = "$dst = $rs1" in { } I do not see any TIED_TO in the generated GenInstrInfo.inc file for the OperandInfo used by the instruction, the question is what am I doing wrong ? 2. I've noticed that TwoOperandAliasConstraint