Displaying 7 results from an estimated 7 matches for "xyzaddrregsregclass".
2016 May 26
3
dumb question about tblgen
...oblem is that my target has separate address and data registers.
The way I’d like to try getting better reg-alloc than I am now is to bring out the difference as
Early as possible, so I have added p16, p32, p64 to the enum in “MachineValueType.h”
And I have called addRegisterClass(MVT::p32, &XyzAddrRegsRegClass);
And I have an override for virtual TargetLowering::getPointerTy() that returns MVT::p32,
And some other minor changes that altogether cause virt-regs that contain pointers
To get my AddrRegs reg-class rather than the “GPR” reg-class that i32 types get.
So far so good, except that llvm-tb...
2016 May 26
0
dumb question about tblgen
...et has separate address and data registers.
> The way I’d like to try getting better reg-alloc than I am now is to bring out the difference as
> Early as possible, so I have added p16, p32, p64 to the enum in “MachineValueType.h”
>
> And I have called addRegisterClass(MVT::p32, &XyzAddrRegsRegClass);
>
> And I have an override for virtual TargetLowering::getPointerTy() that returns MVT::p32,
>
> And some other minor changes that altogether cause virt-regs that contain pointers
> To get my AddrRegs reg-class rather than the “GPR” reg-class that i32 types get.
>
>...
2016 May 26
2
dumb question about tblgen
...te address and
> data registers.
> The way I’d like to try getting better reg-alloc than I am now is to bring
> out the difference as
> Early as possible, so I have added p16, p32, p64 to the enum in
> “MachineValueType.h”
>
> And I have called addRegisterClass(MVT::p32, &XyzAddrRegsRegClass);
>
> And I have an override for virtual TargetLowering::getPointerTy() that
> returns MVT::p32,
>
> And some other minor changes that altogether cause virt-regs that contain
> pointers
> To get my AddrRegs reg-class rather than the “GPR” reg-class that i32
> types get....
2016 May 26
0
dumb question about tblgen
...oblem is that my target has separate address and data registers.
The way I’d like to try getting better reg-alloc than I am now is to bring out the difference as
Early as possible, so I have added p16, p32, p64 to the enum in “MachineValueType.h”
And I have called addRegisterClass(MVT::p32, &XyzAddrRegsRegClass);
And I have an override for virtual TargetLowering::getPointerTy() that returns MVT::p32,
And some other minor changes that altogether cause virt-regs that contain pointers
To get my AddrRegs reg-class rather than the “GPR” reg-class that i32 types get.
So far so good, except that llvm-tb...
2016 May 26
1
dumb question about tblgen
...data registers.
>
> The way I’d like to try getting better reg-alloc than I am now is to bring
> out the difference as
>
> Early as possible, so I have added p16, p32, p64 to the enum in
> “MachineValueType.h”
>
>
>
> And I have called addRegisterClass(MVT::p32, &XyzAddrRegsRegClass);
>
>
>
> And I have an override for virtual TargetLowering::getPointerTy() that
> returns MVT::p32,
>
>
>
> And some other minor changes that altogether cause virt-regs that contain
> pointers
>
> To get my AddrRegs reg-class rather than the “GPR” reg-class...
2016 May 26
0
dumb question about tblgen
Hi Peter,
I would recommend looking into the implementation of the matcher if you want to add more builtin types:
utils/TableGen//DAGISelMatcherGen.cpp
That being said, you can define your own types without having to go through that hassle.
E.g., from AArch64
def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> {
let ParserMatchClass =
2016 May 26
2
dumb question about tblgen
Dumb question about llvm-tblgen for "XyzGenInstrInfo.inc"
If I have a pattern in my dot-td-file like this
[(set i32:$dst (add i32:$rs1, i32:$rs2))]
The question is where does the token "i32" come from,
I don't see any definitions for i1, i8, i16, i32, ... in
include/llvm/Target/*.td
while I do see definitions for tokens like