Displaying 2 results from an estimated 2 matches for "xxx_mul".
2012 May 11
2
[LLVMdev] TableGen pattern for negated operand
...hing *any* opcode (or
even some subset), not just MUL, with a FNEG'd operand? I expect I can
define a PatFrag:
def fneg_su : PatFrag<(ops node:$val), (fneg node:$val), [{ return
N->hasOneUse(); }]>;
and then use that in each target instruction patten in XXXInstrInfo.td, such as:
def XXX_MUL : XXXInst<
(outs GPR32:$dst),
(ins GPR32:$src1, GPR32:$src2),
"mul $dst, -$src1, $src2",
[(set $dst, (mul (fneg_su GPR32:$src1), GPR32:$src2))]>;
but I would like to believe there's a way to do this with a Pattern<>
definition instead, with help from PatFrag a...
2012 May 11
0
[LLVMdev] TableGen pattern for negated operand
...>;
AFAIK, you don't need to verify for hasOneUse() because the instruction
selector will do it for you. Also, it's too restrictive if fneg_su is
used alone in some other matching rule.
> and then use that in each target instruction patten in XXXInstrInfo.td, such as:
>
> def XXX_MUL : XXXInst<
> (outs GPR32:$dst),
> (ins GPR32:$src1, GPR32:$src2),
> "mul $dst, -$src1, $src2",
> [(set $dst, (mul (fneg_su GPR32:$src1), GPR32:$src2))]>;
>
> but I would like to believe there's a way to do this with a Pattern<>
> defini...