Displaying 4 results from an estimated 4 matches for "xu3".
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2016 Jul 15
2
Recompile (and re-link) a function at runtime using ORC JIT for an ARM platform
Hi,
We are making the move from legacy JIT (llvm-3.5.x) to ORC JIT and I am
looking to recompile (and re-link) functions at runtime for an ARM
platform (Odroid XU3) . I looked at OrcLazyJIT.cpp as a starting point.
However, after going through the code, it appears that the
createCompileCallbackMgr (llvm-3.8.0) /
createLocalCompileCallbackManager (llvm-git) do not support an ARM
triple yet.
Does anyone know if ARM will be supported in the future and/or po...
2015 Sep 07
2
POssible bug in the Arm code generator
Hi Erik,
> GHC does not generate or use thumb instructions
From you assembly dump, looks like the instructions are 2 bytes long,
meaning it's Thumb code not ARM.
- Denis.
> Owen Shepherd wrote:
>
>> Pay closer attention to the instruction descriptions on the page you linked
>> above:
>>
>> LDR{*type*}{*cond*}*Rt*, [*Rn* {, #*offset*}] ; immediate
2017 Nov 13
0
[PATCH RFC v3 0/6] x86/idle: add halt poll support
From: Yang Zhang <yang.zhang.wz at gmail.com>
Some latency-intensive workload have seen obviously performance
drop when running inside VM. The main reason is that the overhead
is amplified when running inside VM. The most cost I have seen is
inside idle path.
This patch introduces a new mechanism to poll for a while before
entering idle state. If schedule is needed during poll, then we
2017 Nov 13
0
[PATCH RFC v3 0/6] x86/idle: add halt poll support
From: Yang Zhang <yang.zhang.wz at gmail.com>
Some latency-intensive workload have seen obviously performance
drop when running inside VM. The main reason is that the overhead
is amplified when running inside VM. The most cost I have seen is
inside idle path.
This patch introduces a new mechanism to poll for a while before
entering idle state. If schedule is needed during poll, then we