Displaying 14 results from an estimated 14 matches for "xstgisd".
2016 Nov 03
2
rotl: undocumented LLVM instruction?
...g0
t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
t6: i64 = sub t4, Constant:i64<1>
t7: i64 = shl Constant:i64<1>, t6
t9: i64 = xor t7, Constant:i64<-1>
t10: i64 = and t2, t9
t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
Combining: t11: i64 = Register %R1
Combining: t10: i64 = and t2, t9
Combining: t9: i64 = xor t7, Constant:i64<-1>
... into: t1...
2016 Nov 03
3
rotl: undocumented LLVM instruction?
...64 %vreg1
>> t6: i64 = sub t4, Constant:i64<1>
>> t7: i64 = shl Constant:i64<1>, t6
>> t9: i64 = xor t7, Constant:i64<-1>
>> t10: i64 = and t2, t9
>> t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
>> t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
>>
>>
>>
>> Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
>>
>> Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
>>
>> Combining: t11: i64 = Register %R1
>>
>> Combining: t10:...
2016 Nov 02
3
rotl: undocumented LLVM instruction?
...g0
t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
t6: i64 = sub t4, Constant:i64<1>
t7: i64 = shl Constant:i64<1>, t6
t9: i64 = xor t7, Constant:i64<-1>
t10: i64 = and t2, t9
t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
Combining: t11: i64 = Register %R1
Combining: t10: i64 = and t2, t9
Combining: t9: i64 = xor t7, Constant:i64<-1>
... into: t1...
2016 Nov 03
2
rotl: undocumented LLVM instruction?
...ub t4, Constant:i64<1>
> t7: i64 = shl Constant:i64<1>, t6
> t9: i64 = xor t7, Constant:i64<-1>
> t10: i64 = and t2, t9
> t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
> t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
>
>
>
> Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
>
> Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
>
> Combining: t11: i64 = Register %R1
>
> Combini...
2016 Jan 15
2
Expanding a PseudoOp and accessing the DAG
On 1/15/2016 1:08 PM, Phil Tomson wrote:
>
> Ah, I see, the defm is a multi-class so I needed to change it to:
>
> def: Pat<(load (XSTGADDR_NORMAL tglobaladdr:$addr)),
> (LOADI64_RI tglobaladdr:$addr, 0)>;
> // Match load from a relocatable address to a load with GRP:
> def: Pat<(load (XSTGADDR_USE_GRP tglobaladdr:$addr)),
> (LOADI64_RI
2016 Jan 15
2
Expanding a PseudoOp and accessing the DAG
...at I would do (based on what I understand about your target so
> far):
>
> Define two additional ISD opcodes, specific to your target. One to denote
> a "normal" address, the other to mean "address using GRP". For example
> (you can invent better names for them): XSTGISD::ADDR_NORMAL and
> XSGTISD::ADDR_USE_GRP. Each of them will take a global address as an
> operand and return an address, and their only function will be to serve as
> a "tag" for the instruction selection algorithm to be able to apply
> different selection patterns to them.
&g...
2016 Jan 13
2
Expanding a PseudoOp and accessing the DAG
...at lists.llvm.org> wrote:
> On 1/13/2016 2:26 PM, Phil Tomson via llvm-dev wrote:
>
>> I've got this PseudoOp defined:
>>
>> def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>]>;
>> def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>;
>>
>>
>> let Constraints = "$dst = $addr" in { //, Uses= [GRP] in {
>> def RelAddr : XSTGPseudo< (outs GPRC:$dst),
>> (ins i64imm:$spoff, i64imm:$addr),
>>...
2016 Jan 15
2
Expanding a PseudoOp and accessing the DAG
On 1/15/2016 2:57 PM, Phil Tomson wrote:
>
>
> I see the following in my SelectCode (in XSTGGenDGISel.inc):
>
>
> /*2235*/ OPC_SwitchOpcode /*2 cases */, 27,
> TARGET_VAL(XSTGISD::ADDR_NORMAL),// ->2266
> /*2239*/ OPC_RecordChild0, // #1 = $addr
> /*2240*/ OPC_MoveChild, 0,
> /*2242*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetGlobalAddress),
> /*2245*/ OPC_MoveParent,
> /*2246*/ OPC_MoveParent,
> /*2247*/...
2016 Jan 07
2
TableGen error message: top-level forms in instruction pattern should have void types
...--------------------------------------------------------------===//
// RELADDR
//===----------------------------------------------------------------------===//
def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0,
1>]>;
def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>;
let Uses= [GRP] in {
def RelAddr : XSTGPseudo< (outs),
(ins GPRC:$spoff, GPRC:$dst),
"! RELADDR $spoff, $dst",
[(XSTGRELADDR G...
2016 Jan 07
2
TableGen error message: top-level forms in instruction pattern should have void types
...elAddr: XSTGRELADDR node requires
>> exactly 2 operands!
>>
>> Which makes some sense as XSTGRELADDR is defined as:
>> def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>,
>> SDTCisSameAs<0, 1>]>;
>> def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>;
>>
>
> The problem is that the pattern that you use in the instruction definition
> cannot have any value. That is, the top node has to consume all values
> produced by the nodes below it. The node XSTGRELADDR does have a value,
> and so it ca...
2016 Jan 07
2
TableGen error message: top-level forms in instruction pattern should have void types
...but now I get:
XSTGInstrInfo.td:902:3: error: In RelAddr: XSTGRELADDR node requires
exactly 2 operands!
Which makes some sense as XSTGRELADDR is defined as:
def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0,
1>]>;
def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>;
Phil
-Krzysztof
>
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
> by The Linux Foundation
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
>...
2016 Jan 13
2
Type inference in TableGen DAG patterns
Given the following definitions:
def SDT_XSTGMVINI : SDTypeProfile<1, 1, [SDTCisInt<0>]>;
def XSTGMVINI : SDNode<"XSTGISD::MVINI", SDT_XSTGMVINI>;
def SDT_RELADDR : SDTypeProfile<1, 2, []>;
def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>;
let Constraints = "$dst = $addr", Uses= [GRP] in {
def RelAddr : XSTGPseudo< (outs GPRC:$dst)...
2016 Jan 08
2
TableGen error message: top-level forms in instruction pattern should have void types
On 1/7/2016 5:54 PM, Phil Tomson wrote:
> I got it to compile by changing to:
> def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>,
> SDTCisSameAs<0, 1>]>;
> def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>;
>
> let Uses= [GRP] in {
> def RelAddr : XSTGPseudo< (outs GPRC:$dst),
> (ins GPRC:$spoff, GPRC:$addr),
> "! RELADDR $spoff, $dst",
>...
2016 Jan 13
2
Expanding a PseudoOp and accessing the DAG
I've got this PseudoOp defined:
def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>]>;
def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>;
let Constraints = "$dst = $addr" in { //, Uses= [GRP] in {
def RelAddr : XSTGPseudo< (outs GPRC:$dst),
(ins i64imm:$spoff, i64imm:$addr),
"! RELADDR $spoff, $...