Displaying 7 results from an estimated 7 matches for "xstginstrinfo".
2016 Jan 13
2
Type inference in TableGen DAG patterns
..."! RELADDR $spoff, $dst",
[(set GPRC:$dst, (XSTGRELADDR
i64:$spoff,
(XSTGMVINI i64:$addr)
)
)]>;
}
When I compile I get:
XSTGInstrInfo.td:903:3: error: In RelAddr: Could not infer all types in
pattern!
def RelAddr : XSTGPseudo< (outs GPRC:$dst),
^
I thought that perhaps I could explicitly add the type in like this:
let Constraints = "$dst = $addr", Uses= [GRP] in {
def RelAddr : XSTGPseud...
2016 Jan 07
2
TableGen error message: top-level forms in instruction pattern should have void types
...[(XSTGRELADDR GPRC:$spoff, GPRC:
>> $dst)]>;
>> }
>>
>>
>>
> Remove the "dst" operand from XSTGRELADDR and try something like
> [(set GPRC:$dst, (XSTGRELADDR GPRC:$spoff))]
>
>
That's better, but now I get:
XSTGInstrInfo.td:902:3: error: In RelAddr: XSTGRELADDR node requires
exactly 2 operands!
Which makes some sense as XSTGRELADDR is defined as:
def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0,
1>]>;
def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_REL...
2016 Jan 07
2
TableGen error message: top-level forms in instruction pattern should have void types
On Thu, Jan 7, 2016 at 1:35 PM, Krzysztof Parzyszek <kparzysz at codeaurora.org
> wrote:
> On 1/7/2016 3:25 PM, Phil Tomson wrote:
>
>>
>> That's better, but now I get:
>>
>> XSTGInstrInfo.td:902:3: error: In RelAddr: XSTGRELADDR node requires
>> exactly 2 operands!
>>
>> Which makes some sense as XSTGRELADDR is defined as:
>> def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>,
>> SDTCisSameAs<0, 1>]>;
>> def XSTGRELADDR...
2016 Jan 15
2
Expanding a PseudoOp and accessing the DAG
...rom a relocatable address to a load with GRP:
> def: Pat<(load (addr_use_grp tglobaladdr:$addr)),
> (load (movimm tglobaladdr:$addr), GRP)>;
>
I'm not entirely sure what to replace 'load' with in the patterns above.
I notice that we have these defm's in our XSTGInstrInfo.td file:
defm LOADI64 : LoadOp< 0b1001010, "load", OpInfo_I64, II_LOAD1 >;
defm LOADF64 : LoadOp< 0b1001010, "load", OpInfo_F64, II_LOAD1 >;
defm LOADI32 : LoadOp< 0b1001010, "load", OpInfo_I32, II_LOAD1 >;
defm LOADF32 : LoadOp< 0b1001010, "...
2016 Jan 13
2
Type inference in TableGen DAG patterns
...t, then?
I have another question about expanding that pseudo op, but I'll post it
separately.
Phil
On Wed, Jan 13, 2016 at 10:26 AM, Krzysztof Parzyszek via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> On 1/13/2016 11:59 AM, Phil Tomson via llvm-dev wrote:
>
>>
>> XSTGInstrInfo.td:908:73: error: expected variable name in dag literal
>>
>> i64:(XSTGMVINI i64:$addr)
>> ^
>> How can this be resolved?
>>
>
> Try (i64 (XSTGMVINI ...))
>
> -Krzysztof
>
> --
&...
2016 Jan 07
2
TableGen error message: top-level forms in instruction pattern should have void types
I'm trying to figure out what this error message means:
error: In RelAddr: Top-level forms in instruction pattern should have void
types
The definitions it's complaining about:
//===----------------------------------------------------------------------===//
// RELADDR
//===----------------------------------------------------------------------===//
def SDT_RELADDR :
2016 Jan 13
2
Expanding a PseudoOp and accessing the DAG
On Wed, Jan 13, 2016 at 2:08 PM, Krzysztof Parzyszek via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> On 1/13/2016 2:26 PM, Phil Tomson via llvm-dev wrote:
>
>> I've got this PseudoOp defined:
>>
>> def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>]>;
>> def XSTGRELADDR :