Displaying 10 results from an estimated 10 matches for "xstg".
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2016 Jan 15
2
Expanding a PseudoOp and accessing the DAG
On 1/15/2016 2:57 PM, Phil Tomson wrote:
>
>
> I see the following in my SelectCode (in XSTGGenDGISel.inc):
>
>
> /*2235*/ OPC_SwitchOpcode /*2 cases */, 27,
> TARGET_VAL(XSTGISD::ADDR_NORMAL),// ->2266
> /*2239*/ OPC_RecordChild0, // #1 = $addr
> /*2240*/ OPC_MoveChild, 0,
> /*2242*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetGlobalAdd...
2016 Aug 22
3
Instruction itineraries and fence/barrier instructions
We improved our instruction itineraries and now we're seeing our testcases
for fence instructions break.
For example, we have this testcase:
@write_me = external global i32
@read_me = external global i32
; Function Attrs: nounwind
define i32 @xstg_intrinsic(i32 %foo) #0 {
entry:
; CHECK: store r0, r1, 0, 32
; CHECK-NEXT: fence 2
%foo.addr = alloca i32, align 4
store i32 %foo, i32* %foo.addr, align 4
%0 = load i32* %foo.addr, align 4
store volatile i32 %0, i32* @write_me, align 4
call void @llvm.xstg.memory.barrier(i32 2, i8...
2016 Nov 02
3
rotl: undocumented LLVM instruction?
We've recently moved our project from LLVM 3.6 to LLVM 3.9. I noticed one
of our code generation tests is breaking in 3.9.
The test is:
; RUN: llc < %s -march=xstg | FileCheck %s
define i64 @bclr64(i64 %a, i64 %b) nounwind readnone {
entry:
; CHECK: bclr r1, r0, r1, 64
%sub = sub i64 %b, 1
%shl = shl i64 1, %sub
%xor = xor i64 %shl, -1
%and = and i64 %a, %xor
ret i64 %and
}
I ran llc with -debug to get a better idea of what's going on and...
2016 Jan 15
2
Expanding a PseudoOp and accessing the DAG
On 1/15/2016 1:08 PM, Phil Tomson wrote:
>
> Ah, I see, the defm is a multi-class so I needed to change it to:
>
> def: Pat<(load (XSTGADDR_NORMAL tglobaladdr:$addr)),
> (LOADI64_RI tglobaladdr:$addr, 0)>;
> // Match load from a relocatable address to a load with GRP:
> def: Pat<(load (XSTGADDR_USE_GRP tglobaladdr:$addr)),
> (LOADI64_RI (MOVIMMZ_I64 tglobaladdr:$addr), GRP)>;
Right.
>...
2016 Jan 13
2
Expanding a PseudoOp and accessing the DAG
I've got this PseudoOp defined:
def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>]>;
def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>;
let Constraints = "$dst = $addr" in { //, Uses= [GRP] in {
def RelAddr : XSTGPseudo< (outs GPRC:$dst),
(ins i64imm:$spoff, i64imm:$addr),...
2016 Aug 22
2
Instruction itineraries and fence/barrier instructions
...eraries and now we're seeing our
> testcases for fence instructions break.
> >
> > For example, we have this testcase:
> >
> > @write_me = external global i32
> > @read_me = external global i32
> >
> > ; Function Attrs: nounwind
> > define i32 @xstg_intrinsic(i32 %foo) #0 {
> > entry:
> > ; CHECK: store r0, r1, 0, 32
> > ; CHECK-NEXT: fence 2
> > %foo.addr = alloca i32, align 4
> > store i32 %foo, i32* %foo.addr, align 4
> > %0 = load i32* %foo.addr, align 4
> > store volatile i32 %0, i3...
2016 Nov 03
2
rotl: undocumented LLVM instruction?
...g0
t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
t6: i64 = sub t4, Constant:i64<1>
t7: i64 = shl Constant:i64<1>, t6
t9: i64 = xor t7, Constant:i64<-1>
t10: i64 = and t2, t9
t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
Combining: t11: i64 = Register %R1
Combining: t10: i64 = and t2, t9
Combining: t9: i64 = xor t7, Constant:i64<-1>
... into:...
2016 Nov 03
3
rotl: undocumented LLVM instruction?
...64 %vreg1
>> t6: i64 = sub t4, Constant:i64<1>
>> t7: i64 = shl Constant:i64<1>, t6
>> t9: i64 = xor t7, Constant:i64<-1>
>> t10: i64 = and t2, t9
>> t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
>> t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
>>
>>
>>
>> Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
>>
>> Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
>>
>> Combining: t11: i64 = Register %R1
>>
>> Combining: t...
2015 Nov 06
2
How does -fPIE get passed from clang to llc when run on a .ll file?
...esulting global_dat_x86_pie.ll file, I see it is
identical to the one where I specified -fPIC (global_dat_x86_pic.ll).
There's no indication of the PIE level in the .ll file.
However, I can see (based on the verbose output) that the PIE Level should
be 2:
"clang-3.6" -cc1 -triple xstg--linux-elf -emit-llvm -disable-free
-main-file-name global_dat.c -mrelocation-model pic -pic-level 2 -pie-level
2 ...
So if I were to pass this .ll file (global_dat_x86_pie.ll) to llc how would
llc know that the PIE Level is 2? Is this an oversight, bug, or expetcted
behaviour with a different wor...
2016 Nov 03
2
rotl: undocumented LLVM instruction?
...ub t4, Constant:i64<1>
> t7: i64 = shl Constant:i64<1>, t6
> t9: i64 = xor t7, Constant:i64<-1>
> t10: i64 = and t2, t9
> t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
> t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
>
>
>
> Combining: t13: ch = XSTGISD::Ret t12, Register:i64 %R1, t12:1
>
> Combining: t12: ch,glue = CopyToReg t0, Register:i64 %R1, t10
>
> Combining: t11: i64 = Register %R1
>
> Comb...