Displaying 1 result from an estimated 1 matches for "xseqpairs".
2019 Oct 12
2
Register allocation constraints
Hi,
I have a problem during my development of a backend. There are some
target instructions with multiple outputs, for example an instructionX with
2 inputs and 2 outputs:
def1, def2 = InstructionX op1, op2
The defs above must be allocated in consecutive target physical registers.
Is it possible to describe the constraints with tablegen and let the
register allocator get all the things