Displaying 9 results from an estimated 9 matches for "xrelease".
Did you mean:
release
2013 Feb 19
9
[LLVMdev] [RFC] Add Intel TSX HLE Support
Hi All,
I'd like to add HLE support in LLVM/clang consistent to GCC's style [1].
HLE from Intel TSX [2] is legacy compatible instruction set extension to
specify transactional region by adding XACQUIRE and XRELEASE prefixes.
To support that, GCC chooses the approach by extending the memory order
flag in __atomic_* builtins with target-specific memory model in high
bits (bit 31-16 for target-specific memory model, bit 15-0 for the
general memory model.) To follow the similar approach, I propose to
change LLVM/...
2013 Feb 19
0
[LLVMdev] [RFC] Add Intel TSX HLE Support
...ael
On Tue, 2013-02-19 at 14:07 -0800, Michael Liao wrote:
> Hi All,
>
> I'd like to add HLE support in LLVM/clang consistent to GCC's style [1].
> HLE from Intel TSX [2] is legacy compatible instruction set extension to
> specify transactional region by adding XACQUIRE and XRELEASE prefixes.
> To support that, GCC chooses the approach by extending the memory order
> flag in __atomic_* builtins with target-specific memory model in high
> bits (bit 31-16 for target-specific memory model, bit 15-0 for the
> general memory model.) To follow the similar approach, I pro...
2013 Feb 19
0
[LLVMdev] [RFC] Add Intel TSX HLE Support
...ael
On Tue, 2013-02-19 at 14:07 -0800, Michael Liao wrote:
> Hi All,
>
> I'd like to add HLE support in LLVM/clang consistent to GCC's style [1].
> HLE from Intel TSX [2] is legacy compatible instruction set extension to
> specify transactional region by adding XACQUIRE and XRELEASE prefixes.
> To support that, GCC chooses the approach by extending the memory order
> flag in __atomic_* builtins with target-specific memory model in high
> bits (bit 31-16 for target-specific memory model, bit 15-0 for the
> general memory model.) To follow the similar approach, I pro...
2013 Feb 19
0
[LLVMdev] [RFC] Add Intel TSX HLE Support
...ael
On Tue, 2013-02-19 at 14:07 -0800, Michael Liao wrote:
> Hi All,
>
> I'd like to add HLE support in LLVM/clang consistent to GCC's style [1].
> HLE from Intel TSX [2] is legacy compatible instruction set extension to
> specify transactional region by adding XACQUIRE and XRELEASE prefixes.
> To support that, GCC chooses the approach by extending the memory order
> flag in __atomic_* builtins with target-specific memory model in high
> bits (bit 31-16 for target-specific memory model, bit 15-0 for the
> general memory model.) To follow the similar approach, I pro...
2013 Feb 19
2
[LLVMdev] [RFC] Add Intel TSX HLE Support
Hi All,
I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. HLE from Intel TSX [2] is legacy compatible instruction set extension to
specify transactional region by adding XACQUIRE and XRELEASE prefixes. To support that, GCC chooses the approach by extending the memory order
flag in __atomic_* builtins with target-specific memory model in high bits (bit 31-16 for target-specific memory model, bit 15-0 for the general memory model.) To follow the similar approach, I propose to
change LLVM/...
2013 Feb 19
0
[LLVMdev] [RFC] Add Intel TSX HLE Support
...11:52 AM, Michael Liao <michael.liao at intel.com> wrote:
> Hi All,
>
> I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. HLE from Intel TSX [2] is legacy compatible instruction set extension to
> specify transactional region by adding XACQUIRE and XRELEASE prefixes. To support that, GCC chooses the approach by extending the memory order
> flag in __atomic_* builtins with target-specific memory model in high bits (bit 31-16 for target-specific memory model, bit 15-0 for the general memory model.) To follow the similar approach, I propose to
> ch...
2013 Feb 28
1
[LLVMdev] [RFC] Add Intel TSX HLE Support
...o <michael.liao at intel.com> wrote:
>
>> Hi All,
>>
>> I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. HLE from Intel TSX [2] is legacy compatible instruction set extension to
>> specify transactional region by adding XACQUIRE and XRELEASE prefixes. To support that, GCC chooses the approach by extending the memory order
>> flag in __atomic_* builtins with target-specific memory model in high bits (bit 31-16 for target-specific memory model, bit 15-0 for the general memory model.) To follow the similar approach, I propose to
>...
2006 May 08
1
Voicemail bomb
I submitted a bug to the tracker
*(*bug<http://bugs.digium.com/view.php?id=6947>) regarding
the 256 character limit when copying a voicemail to a list of mail boxes.
The bug was closed with this note:
"Fixed in 1.2 branch, merged to trunk."
Could someone explain to me what that means... in English?
I searched the release notes of the newest asterisk version to see if this
bug
2006 Dec 10
3
Asterisk from Debian Packages
Hi all,
I've gotten asterisk installed on Debian only to realize that the
packaged version is 1.0.7. Is there a reason why they're not up to a
1.2.x release? I'm building a system for production and I'm wondering
if I should remain at this old version or if there are any serious
issues with 1.2.13 on Debian? Should I be able to do an apt-get from
unstable and get 1.2.13 and