Displaying 3 results from an estimated 3 matches for "xor2".
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2010 Sep 05
2
[LLVMdev] Possible missed optimization?
...a look at this yourself, the issue is easy to
> reproduce with Thumb1:
Thanks, Eli. Nice catch!
This IR:
target triple = "thumbv5-u-u"
define arm_aapcscc i64 @foo(i64 %a, i64 %b) nounwind readnone {
entry:
%xor = xor i64 %a, 18 ; <i64> [#uses=1]
%xor2 = xor i64 %xor, %b ; <i64> [#uses=1]
ret i64 %xor2
}
produces these instructions before coalescing:
4L %reg16387<def> = COPY %R3<kill>
12L %reg16386<def> = COPY %R2<kill>
28L %reg16384<def> = COPY %R0<kill>
36L %r...
2010 Sep 05
0
[LLVMdev] Possible missed optimization?
On Sat, Sep 4, 2010 at 1:31 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:
>
> On Sep 4, 2010, at 11:21 AM, Borja Ferrer wrote:
>
>> I've noticed this pattern happening with other operators aswell, but used xor in this example. As i said before, i tried with different register allocation orders, but it will produce always the same result. GCC is emitting longer
2010 Sep 04
3
[LLVMdev] Possible missed optimization?
On Sep 4, 2010, at 11:21 AM, Borja Ferrer wrote:
> I've noticed this pattern happening with other operators aswell, but used xor in this example. As i said before, i tried with different register allocation orders, but it will produce always the same result. GCC is emitting longer code, but since LLVM is so nearer to the optimal code sequence i wanted to reach it.
In LLVM, copies are