search for: xop

Better be quick! I am adding FMA4 and XOP now, and if you contribute code before I do, you can spare yourself some XOP merging. - Jan ----- Original Message ----- > From: David A. Greene <greened at obbligato.org> > To: Benjamin Kramer <benny.kra at googlemail.com> > Cc: llvmdev at cs.uiuc.edu > Sent: Thursday,...

...to support this cpu ? >> >> I don't know. Hopefully someone who knows something about this will comment. > > I added a basic description for bdver1 and bdver2 in r145493. > LLVM doesn't know many of bulldozer's new instructions though. We have implementations for XOP. Again, I'll be pushing it back as soon as we get 3.0 merged. That will take a bit of effort as we have to resolve various AVX conflicts. -Dave

Jan Sjodin <jan_sjodin at yahoo.com> writes: > Better be quick! I am adding FMA4 and XOP now, and if you contribute > code before I do, you can spare yourself some XOP merging. Go ahead. We're not going to get there soon enough. :( -Dave

...sse2.pcmpeq.* - we have almost no test cases for this x86.sse2.pcmpgt.* - we no test cases for this x86.avx2.pcmpeq.* - we have no test cases x86.avx2.pcmpgt.* - we have no test cases for this x86.avx.vpermil.* - we do test this 3.2 added upgrade for: x86.avx.movnt.* - we have tests for this x86.xop.vpcom* - we have tests for this x86.sse41.ptest.* had its signature chagned and we upgrade from the old signature. We don't have tests for the old signature. x86.xop.vfrcz.ss/sd had an argument dropped that we upgrade for. We don't have any tests for the old signature. 3.3 had no upgrades...

...r pge mca cmov pat pse36 clflush > mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb lm rep_good nopl > extd_apicid pni pclmulqdq ssse3 fma cx16 sse4_1 sse4_2 x2apic popcnt aes xsave > avx f16c hypervisor lahf_lm cmp_legacy svm cr8_legacy abm sse4a misalignsse > 3dnowprefetch osvw xop fma4 tbm arat npt nrip_save tsc_adjust bmi1 > > whereas in a (working) -cpu qemu64 guest, they look like this: > > fpu de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx > fxsr sse sse2 ht syscall nx lm nopl pni cx16 x2apic popcnt hypervisor lahf_lm > cm...

...r pge mca cmov pat pse36 clflush > mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb lm rep_good nopl > extd_apicid pni pclmulqdq ssse3 fma cx16 sse4_1 sse4_2 x2apic popcnt aes xsave > avx f16c hypervisor lahf_lm cmp_legacy svm cr8_legacy abm sse4a misalignsse > 3dnowprefetch osvw xop fma4 tbm arat npt nrip_save tsc_adjust bmi1 > > whereas in a (working) -cpu qemu64 guest, they look like this: > > fpu de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx > fxsr sse sse2 ht syscall nx lm nopl pni cx16 x2apic popcnt hypervisor lahf_lm > cm...

On 30.11.2011, at 08:33, Duncan Sands wrote: > Hi Jan, > >> if I compile with dragonegg and -march=native I get this message: >> 'bdver1' is not a recognized processor for this target (ignoring processor) > > this is coming directly from LLVM which doesn't know about bulldozer yet. > >> Is there any plan to support this cpu ? > > I don't

...truction requires the REX.W it to be set. hasLockPrefix - Indicates the instruction should be encoded with a 0xF0 lock prefix. hasREPPrefix - Indicates the instruction should be encoded with a 0xF3 rep prefix. OpcEnc - Which encoding scheme this instruction uses. Normal, VEX, EVEX, or XOP. VEX_WPrefix - Controls the value of the VEX.W bit in the encoder also tells the disassembler which instructions ignore VEX.W. hasVEX_4V - Does this instruction use VEX.vvvv hasVEX_L - Should this instruction be encoded with VEX.L=1 ignoresVEX_L - Tells the disassembler that VEX...

I am attempting to create an instruction which takes a single 64-bit immediate. This doesn't seem like a thing that would exist already (because who needs an instruction which just takes an immediate?) How might I implement this easily? Perhaps I could use a format which encodes a register, which is then unused? Thanks for the help. Gus -------------- next part -------------- An HTML

...cases for this > x86.sse2.pcmpgt.* - we no test cases for this > x86.avx2.pcmpeq.* - we have no test cases > x86.avx2.pcmpgt.* - we have no test cases for this > x86.avx.vpermil.* - we do test this > > 3.2 added upgrade for: > x86.avx.movnt.* - we have tests for this > x86.xop.vpcom* - we have tests for this > x86.sse41.ptest.* had its signature chagned and we upgrade from the old > signature. We don't have tests for the old signature. > x86.xop.vfrcz.ss/sd had an argument dropped that we upgrade for. We don't > have any tests for the old signature. &...

...2.pcmpgt.* - we no test cases for this >> x86.avx2.pcmpeq.* - we have no test cases >> x86.avx2.pcmpgt.* - we have no test cases for this >> x86.avx.vpermil.* - we do test this >> >> 3.2 added upgrade for: >> x86.avx.movnt.* - we have tests for this >> x86.xop.vpcom* - we have tests for this >> x86.sse41.ptest.* had its signature chagned and we upgrade from the old >> signature. We don't have tests for the old signature. >> x86.xop.vfrcz.ss/sd had an argument dropped that we upgrade for. We don't >> have any tests for the...

...mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb lm rep_good nopl extd_apicid pni pclmulqdq ssse3 fma cx16 sse4_1 sse4_2 x2apic popcnt aes xsave avx f16c hypervisor lahf_lm cmp_legacy svm cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw xop fma4 tbm arat npt nrip_save tsc_adjust bmi1 whereas in a (working) -cpu qemu64 guest, they look like this: fpu de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx lm nopl pni cx16 x2apic popcnt hypervisor lahf_lm cmp_legacy svm abm sse4a I trie...

...mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb lm rep_good nopl extd_apicid pni pclmulqdq ssse3 fma cx16 sse4_1 sse4_2 x2apic popcnt aes xsave avx f16c hypervisor lahf_lm cmp_legacy svm cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw xop fma4 tbm arat npt nrip_save tsc_adjust bmi1 whereas in a (working) -cpu qemu64 guest, they look like this: fpu de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx lm nopl pni cx16 x2apic popcnt hypervisor lahf_lm cmp_legacy svm abm sse4a I trie...

...ases for this > x86.sse2.pcmpgt.* - we no test cases for this > x86.avx2.pcmpeq.* - we have no test cases > x86.avx2.pcmpgt.* - we have no test cases for this > x86.avx.vpermil.* - we do test this > > 3.2 added upgrade for: > x86.avx.movnt.* - we have tests for this > x86.xop.vpcom* - we have tests for this > x86.sse41.ptest.* had its signature chagned and we upgrade from the old signature. We don't have tests for the old signature. > x86.xop.vfrcz.ss/sd had an argument dropped that we upgrade for. We don't have any tests for the old signature. > >...

...sse2.pcmpeq.* - we have almost no test cases for this x86.sse2.pcmpgt.* - we no test cases for this x86.avx2.pcmpeq.* - we have no test cases x86.avx2.pcmpgt.* - we have no test cases for this x86.avx.vpermil.* - we do test this 3.2 added upgrade for: x86.avx.movnt.* - we have tests for this x86.xop.vpcom* - we have tests for this x86.sse41.ptest.* had its signature chagned and we upgrade from the old signature. We don't have tests for the old signature. x86.xop.vfrcz.ss/sd had an argument dropped that we upgrade for. We don't have any tests for the old signature. 3.3 had no upgrades...

...cases for this > x86.sse2.pcmpgt.* - we no test cases for this > x86.avx2.pcmpeq.* - we have no test cases > x86.avx2.pcmpgt.* - we have no test cases for this > x86.avx.vpermil.* - we do test this > > 3.2 added upgrade for: > x86.avx.movnt.* - we have tests for this > x86.xop.vpcom* - we have tests for this > x86.sse41.ptest.* had its signature chagned and we upgrade from the old > signature. We don't have tests for the old signature. > x86.xop.vfrcz.ss/sd had an argument dropped that we upgrade for. We don't > have any tests for the old signature. &...

...quot;llvmdev at cs.uiuc.edu" <llvmdev at cs.uiuc.edu> > Sent: Thursday, December 1, 2011 2:48 PM > Subject: Re: [LLVMdev] bdver1 cpu(bulldozer) support with dragonegg > > Jan Sjodin <jan_sjodin at yahoo.com> writes: > >> Better be quick! I am adding FMA4 and XOP now, and if you contribute >> code before I do, you can spare yourself some XOP merging. > > Go ahead.  We're not going to get there soon enough.  :( > >                             -Dave >

...r()); } On this windows laptop that I am testing on, I get these values: target_specific_cpu_args: skylake target_specific_features: +sse2,+cx16,-tbm,-avx512ifma,-avx512dq,-fma4,+prfchw,+bmi2,+xsavec,+fsgsbase,+popcnt,+aes,+xsaves,-avx512er,-avx512vpopcntdq,-clwb,-avx512f,-clzero,-pku,+mmx,-lwp,-xop,+rdseed,-sse4a,-avx512bw,+clflushopt,+xsave,-avx512vl,-avx512cd,+avx,-rtm,+fma,+bmi,+rdrnd,-mwaitx,+sse4.1,+sse4.2,+avx2,+sse,+lzcnt,+pclmul,-prefetchwt1,+f16c,+ssse3,+sgx,+cmov,-avx512vbmi,+movbe,+xsaveopt,-sha,+adx,-avx512pf,+sse3 It successfully creates a binary, but the binary when run crashe...

...ush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc art rep_good nopl nonstop_tsc extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 popcnt aes xsave avx f16c lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs xop skinit wdt lwp fma4 tce nodeid_msr tbm topoext perfctr_core perfctr_nb arat cpb hw_pstate npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold bmi1 bogomips : 7023.90 TLB size : 1536 4K pages clflush size : 64 cache_alignment : 64 address sizes : 4...

...>>> mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb lm rep_good nopl >>> extd_apicid pni pclmulqdq ssse3 fma cx16 sse4_1 sse4_2 x2apic popcnt aes xsave >>> avx f16c hypervisor lahf_lm cmp_legacy svm cr8_legacy abm sse4a misalignsse >>> 3dnowprefetch osvw xop fma4 tbm arat npt nrip_save tsc_adjust bmi1 >>> >>> whereas in a (working) -cpu qemu64 guest, they look like this: >>> >>> fpu de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx >>> fxsr sse sse2 ht syscall nx lm nopl pni cx16...