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...roach (when we don't create regclass and just hard-code it in .td) > > But I still receive strange errors. I received DAG which I happy with > (DAG here: http://goo.gl/62tpkk), but everything goes broken on > scheduling. > > I had to chain mine nodes, because otherwise nodes xmac and srxacc got > removed on first combine. But since they are chained, they have > MVT::Other return type, and that causes strange crash inside func > GetCostFor in ScheduleDAGRRList.cpp: > > Def RegClass = TLI->getRepRegClassFor(VT)->getID(); > When VT is MVT::Other it r...

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Hi, Yes, that's what I would do. If you want LLVM and the register allocator to also know that the instruction explicitly defines the register, I would designate the register into it's own register class and have your instruction write to that class (and there will be only a single option for RA). cheers, Sam Sam Parker Research Student Electronic Systems Design Group Loughborough