Displaying 6 results from an estimated 6 matches for "xform_base_r3xo_swap".
2012 Jul 24
2
[LLVMdev] Instruction Encodings in TableGen
...: XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1012 "and $rA, $rS, $rB", IntSimple,
1013 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
Okay, so rA, rS, and rB are register operands.
The TableGen classes are defined as:
315 class XForm_base_r3xo_swapped
316 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
317 InstrItinClass itin>
318 : I<opcode, OOL, IOL, asmstr, itin> {
319 bits<5> A;
320 bits<5> RST;
321 bits<5> B;
322
323 bit RC = 0; // set by isDOT
324
325...
2012 Jul 24
2
[LLVMdev] Instruction Encodings in TableGen
...12 "and $rA, $rS, $rB", IntSimple,
> > 1013 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
> >
> > Okay, so rA, rS, and rB are register operands.
> >
> > The TableGen classes are defined as:
> >
> > 315 class XForm_base_r3xo_swapped
> > 316 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string
> asmstr,
> > 317 InstrItinClass itin>
> > 318 : I<opcode, OOL, IOL, asmstr, itin> {
> > 319 bits<5> A;
> > 320 bits<5> RST;
> > 321 b...
2012 Jul 24
0
[LLVMdev] Instruction Encodings in TableGen
...ins GPRC:$rS, GPRC:$rB),
> 1012 "and $rA, $rS, $rB", IntSimple,
> 1013 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
>
> Okay, so rA, rS, and rB are register operands.
>
> The TableGen classes are defined as:
>
> 315 class XForm_base_r3xo_swapped
> 316 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
> 317 InstrItinClass itin>
> 318 : I<opcode, OOL, IOL, asmstr, itin> {
> 319 bits<5> A;
> 320 bits<5> RST;
> 321 bits<5> B;
> 322
> 323...
2012 Jul 25
2
[LLVMdev] Instruction Encodings in TableGen
...and $rA, $rS, $rB", IntSimple,
>> > 1013 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
>> >
>> > Okay, so rA, rS, and rB are register operands.
>> >
>> > The TableGen classes are defined as:
>> >
>> > 315 class XForm_base_r3xo_swapped
>> > 316 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string
>> asmstr,
>> > 317 InstrItinClass itin>
>> > 318 : I<opcode, OOL, IOL, asmstr, itin> {
>> > 319 bits<5> A;
>> > 320 bits<5>...
2012 Jul 25
0
[LLVMdev] Instruction Encodings in TableGen
...12 "and $rA, $rS, $rB", IntSimple,
> > 1013 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
> >
> > Okay, so rA, rS, and rB are register operands.
> >
> > The TableGen classes are defined as:
> >
> > 315 class XForm_base_r3xo_swapped
> > 316 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
> > 317 InstrItinClass itin>
> > 318 : I<opcode, OOL, IOL, asmstr, itin> {
> > 319 bits<5> A;
> > 320 bits<5> RST;
> > 321 bits&l...
2012 Jul 27
0
[LLVMdev] Instruction Encodings in TableGen
...1013 [(set GPRC:$rA, (and GPRC:$rS,
> >> > GPRC:$rB))]>;
> >> >
> >> > Okay, so rA, rS, and rB are register operands.
> >> >
> >> > The TableGen classes are defined as:
> >> >
> >> > 315 class XForm_base_r3xo_swapped
> >> > 316 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
> >> > string
> >> asmstr,
> >> > 317 InstrItinClass itin>
> >> > 318 : I<opcode, OOL, IOL, asmstr, itin> {
> >> > 319 bits&...