search for: xform_1

...ith a lot of "if (!isDarwin)". There are some places where I need help before saying the port is complete. I attached the diff file as a reference 1) In order to generate a creqv instruction before a vararg call, I created a new instruction in PPCInstrInfo.td: SETCR which uses the new XForm_1_ext format. It does not use the XForm_1 format because I wanted to give only one register as operand. I'm not sure if this is the correct way to do this, but it works. 2) Line 369 of PPCInstrInfo.td, we declare the non-callee saved registers. However, Linux and Darwin do not have the same se...

...uot;. > > There are some places where I need help before saying the port is > complete. I attached the diff file as a reference > > 1) In order to generate a creqv instruction before a vararg call, I > created a new instruction in PPCInstrInfo.td: SETCR which > uses the new XForm_1_ext format. It does not use the XForm_1 format > because I wanted to give only one register as operand. > I'm not sure if this is the correct way to do this, but it works. > > 2) Line 369 of PPCInstrInfo.td, we declare the non-callee saved > registers. However, Linux and Darw...

...n { -def STDCX : Pseudo<(outs), (ins G8RC:$rS, memrr:$dst, i32imm:$label), - "stdcx. $rS, $dst\n\tbne- La${label}_entry\nLa${label}_exit:", - [(PPCstcx G8RC:$rS, xoaddr:$dst, imm:$label)]>; +// Instructions to support atomic operations +def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr), + "ldarx $rD, $ptr", LdStLDARX, + [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>; -def CMP_UNRESd : Pseudo<(outs), (ins G8RC:$rA, G8RC:$rB, i32imm:$label), - "cmpd $rA, $rB\n\...

...s where I need help before saying the port is >> complete. I attached the diff file as a reference >> >> >> 1) In order to generate a creqv instruction before a vararg call, I >> created a new instruction in PPCInstrInfo.td: SETCR which >> >> uses the new XForm_1_ext format. It does not use the XForm_1 format >> because I wanted to give only one register as operand. >> >> I'm not sure if this is the correct way to do this, but it works. >> >> >> 2) Line 369 of PPCInstrInfo.td, we declare the non-callee saved >&gt...

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

...n { -def STDCX : Pseudo<(outs), (ins G8RC:$rS, memrr:$dst, i32imm:$label), - "stdcx. $rS, $dst\n\tbne- La${label}_entry\nLa${label}_exit:", - [(PPCstcx G8RC:$rS, xoaddr:$dst, imm:$label)]>; +// Instructions to support atomic operations +def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr), + "ldarx $rD, $ptr", LdStLDARX, + [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>; -def CMP_UNRESd : Pseudo<(outs), (ins G8RC:$rA, G8RC:$rB, i32imm:$label), - "cmpd $rA, $rB\n\...

Hi Gary, This does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const

Evan Cheng wrote: > How about? > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > &PPC:G8RCRegClass; > unsigned TmpReg = RegInfo.createVirtualRegister(RC); I tried something like that yesterday: const TargetRegisterClass *RC = is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; but I kept getting this error no matter how I arranged it:

You need to insert new basic blocks and update CFG to accomplish this. There is a hackish way to do this right now. Add a pseudo instruction to represent this operation and mark it usesCustomDAGSchedInserter. This means the intrinsic is mapped to a single (pseudo) node. But it is then expanded into instructions that can span multiple basic blocks. See

...n { -def STDCX : Pseudo<(outs), (ins G8RC:$rS, memrr:$dst, i32imm:$label), - "stdcx. $rS, $dst\n\tbne- La${label}_entry\nLa${label}_exit:", - [(PPCstcx G8RC:$rS, xoaddr:$dst, imm:$label)]>; +// Instructions to support atomic operations +def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr), + "ldarx $rD, $ptr", LdStLDARX, + [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>; -def CMP_UNRESd : Pseudo<(outs), (ins G8RC:$rA, G8RC:$rB, i32imm:$label), - "cmpd $rA, $rB\n\...

Would it be acceptable to change MachineInstr::getRegInfo from private to public so I can use it from PPCTargetLowering::EmitInstrWithCustomInserter? Cheers, Gary Evan Cheng wrote: > Look for createVirtualRegister. These are examples in > PPCISelLowering.cpp. > > Evan > On Jul 8, 2008, at 8:24 AM, Gary Benson wrote: > > > Hi Evan, > > > > Evan Cheng wrote:

Chris Lattner wrote: > On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: > > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: > > $label), > > "cmpw $rA, $rB\n\tbne- La${label}_exit", > > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: > > $label)]>; > > } > > > > ...and

...n { -def STDCX : Pseudo<(outs), (ins G8RC:$rS, memrr:$dst, i32imm:$label), - "stdcx. $rS, $dst\n\tbne- La${label}_entry\nLa${label}_exit:", - [(PPCstcx G8RC:$rS, xoaddr:$dst, imm:$label)]>; +// Instructions to support atomic operations +def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr), + "ldarx $rD, $ptr", LdStLDARX, + [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>; -def CMP_UNRESd : Pseudo<(outs), (ins G8RC:$rA, G8RC:$rB, i32imm:$label), - "cmpd $rA, $rB\n\...

...+ lib/Target/PowerPC/PPCInstrInfo.td (working copy) @@ -531,8 +531,8 @@ PPC970_DGroup_Single; // Atomic operations. -def LWARX : Pseudo<(outs GPRC:$rD), (ins memrr:$ptr, i32imm:$label), - "\nLa${label}_entry:\n\tlwarx $rD, $ptr", +def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$ptr, i32imm:$label), + "\nLa${label}_entry:\n\tlwarx $rD, $ptr", LdStLWARX, [(set GPRC:$rD, (PPClarx xoaddr:$ptr, imm:$label))]>; let Defs = [CR0] in {

...t your pieces will be applied in a timely fashion :). This will also let you get pieces in before the whole thing is "done". > 1) In order to generate a creqv instruction before a vararg call, I created a > new instruction in PPCInstrInfo.td: SETCR which > uses the new XForm_1_ext format. It does not use the XForm_1 format because I > wanted to give only one register as operand. > I'm not sure if this is the correct way to do this, but it works. Yep, that's the right way to go. > 2) Line 369 of PPCInstrInfo.td, we declare the non-callee saved register...