Displaying 7 results from an estimated 7 matches for "xfeature_mask".
Did you mean:
feature_mask
2013 Nov 19
6
[PATCH 2/5] X86 architecture instruction set extension definiation
...p; XSTATE_FP) ||
- ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE)) ||
- ((xcr0_accum & XSTATE_YMM) && !(xcr0_accum & XSTATE_SSE)) )
+ !valid_xcr0(xcr0) ||
+ !valid_xcr0(xcr0_accum) )
return -EINVAL;
if ( xcr0_accum & ~xfeature_mask )
@@ -351,10 +364,7 @@ int handle_xsetbv(u32 index, u64 new_bv)
if ( index != XCR_XFEATURE_ENABLED_MASK )
return -EOPNOTSUPP;
- if ( (new_bv & ~xfeature_mask) || !(new_bv & XSTATE_FP) )
- return -EINVAL;
-
- if ( (new_bv & XSTATE_YMM) && !(new_bv &am...
2010 Oct 29
1
[Patch 0/4] Refining Xsave/Xrestore support - Version 2
Hi, Keir,
The following patches refines Xen support for CPU Xsave/Xrestore
support. There are four patches included.
Patch 1/4:
Cleaning up existing Xsave code in Xen.
Replace xfeature_low and xfeature_high with a u64 variable
xfeature_mask.
In structure hvm_vcpu, rename xfeature_mask to xcr0
Provide EDX:EAX with all bits set to 1 for XSAVE and XRSTOR as
spec recommends
Patch 2/4:
Adding Xsave/Xrestore support for PV guests. Feature is exposed
via CPUID. XSETBV is trapped and emulated by Xen (via GP#).
Patch 3/4:
E...
2013 Nov 25
0
[PATCH 2/4 V2] X86: enable support for new ISA extensions
...p; XSTATE_FP) ||
- ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE)) ||
- ((xcr0_accum & XSTATE_YMM) && !(xcr0_accum & XSTATE_SSE)) )
+ !valid_xcr0(xcr0) ||
+ !valid_xcr0(xcr0_accum) )
return -EINVAL;
if ( xcr0_accum & ~xfeature_mask )
@@ -351,10 +369,7 @@ int handle_xsetbv(u32 index, u64 new_bv)
if ( index != XCR_XFEATURE_ENABLED_MASK )
return -EOPNOTSUPP;
- if ( (new_bv & ~xfeature_mask) || !(new_bv & XSTATE_FP) )
- return -EINVAL;
-
- if ( (new_bv & XSTATE_YMM) && !(new_bv &am...
2010 Aug 31
2
[PATCH 2/3 v2] XSAVE/XRSTOR: fix frozen states
If a guest sets a state and dirties the state, but later temporarily clears the state, and at this time if this vcpu is scheduled out, then other vcpus may corrupt the state before the vcpu is scheduled in again, thus the state cannot be restored correctly. To solve this issue, this patch save/restore all states unconditionally on vcpu context switch.
Signed-off-by: Weidong Han
2013 Jun 04
12
[PATCH 0/4] XSA-52..54 follow-up
The first patch really isn''t as much of a follow-up than what triggered
the security issues to be noticed in the first place.
1: x86: preserve FPU selectors for 32-bit guest code
2: x86: fix XCR0 handling
3: x86/xsave: adjust state management
4: x86/fxsave: bring in line with recent xsave adjustments
The first two I would see as candidates for 4.3 (as well as
subsequent backporting,
2012 Sep 04
2
[PATCH] valgrind: Support for ioctls used by Xen toolstack processes.
..._READ("XEN_DOMCTL_set_cpuid",
+ (Addr)&domctl->u.cpuid, sizeof(domctl->u.cpuid));
+ break;
+
+ case XEN_DOMCTL_getvcpuextstate:
+ __PRE_XEN_DOMCTL_READ(getvcpuextstate, vcpuextstate, vcpu);
+ __PRE_XEN_DOMCTL_READ(getvcpuextstate, vcpuextstate, xfeature_mask);
+ __PRE_XEN_DOMCTL_READ(getvcpuextstate, vcpuextstate, size);
+ __PRE_XEN_DOMCTL_READ(getvcpuextstate, vcpuextstate, buffer);
+ break;
+
+ default:
+ bad_subop(tid, layout, arrghs, status, flags,
+ "__HYPERVISOR_domctl", domctl->cmd);
+ break...
2011 Feb 07
0
[xen-unstable test] 5665: regressions - FAIL
...-------------------------------------------------
changeset: 22878:7ada6faef565
tag: tip
user: Keir Fraser <keir@xen.org>
date: Sun Feb 06 17:26:31 2011 +0000
hvm: fix XSAVE leaf 0 EBX size calculation
Fixes a size calculation bug when enabled bits in XFEATURE_MASK (xcr0)
aren''t contiguous.
Current for_loop will stop when xcr0 feature bit is 0. But in reality,
the bits can be non-contiguous. One example is that LWP is bit 62 on
AMD platform. This patch iterates through all bits to calculate the
size for enabled features....