Displaying 2 results from an estimated 2 matches for "x86typeinfo".
2016 Oct 12
2
Generate Register Indirect mode instruction
...32* %a, align 4
%add = add i32 %0, 3
store i32 %add, i32* %a, align 4
ret void
}
On x86, this gets turned into:
addl $3, (%rdi)
retq
From X86InstrArithmetic.td:
// BinOpMI8_RMW - Instructions like "add [mem], imm8".
class BinOpMI8_RMW<string mnemonic, X86TypeInfo typeinfo,
SDPatternOperator opnode, Format f>
: BinOpMI8<mnemonic, typeinfo, f,
[(store (opnode (load addr:$dst),
typeinfo.Imm8Operator:$src), addr:$dst),
(implicit EFLAGS)]>;
-Eli
--
Employee of Qualcomm...
2016 Oct 10
8
Generate Register Indirect mode instruction
Hi All,
I am new to llvm backend. I am trying out few examples to understand
backend codegen. I have ported llvm LEG @
https://github.com/frasercrmck/llvm-leg to llvm 3.9 successfully.
Currently, the LEG instructions are RISC load-store type instruction. I
want to generate some instructions for register indirect mode, like
following:
IR:
@a = local_unnamed_addr global i32 0, align 4
@b =