search for: x86sselevel

...tionDAG phase in file "X86ISelLowering.cpp", i checked in one of the function what is the subtarget feature by calling few routines of Subtarget. Subtarget->hasMMX() ------ true Subtarget->hasSSE1() ------ true Subtarget->hasSSE2() ------ true These functions just compare the X86SSELevel with subtarget enum values like MMX, SSE1, SSE2 etc. hasMMX() { return X86SSELevel >= MMX}; // similar for others Now, enum values start from MMX and goes on increasing with SSE1, SSE2, etc. For the above test case, the X86SSELevel is set to SSE2, which is confusing, since i have explicitly...

..."Enable AVX instructions", [FeatureSSE42, FeatureYMM, FeatureVEX]>; YMM, VEX and FMA are all separate features detectable through CPUID. The key question here is whether making X86AVX a boolean feature flag separate from X86SSELevel is reasonable. As I've been going along I've added feature flags for SSE4a and SSE5. These really do need to be separate feature flags because having SSE4a and/or SSE5 does not imply that you have SSE4.2 or SSE4.1. So they can't be part of the X86SSELevel scheme. Opinions on whet...

...X instructions", > [FeatureSSE42, FeatureYMM, > FeatureVEX]>; > > YMM, VEX and FMA are all separate features detectable through CPUID. > > The key question here is whether making X86AVX a boolean feature > flag separate > from X86SSELevel is reasonable. It sounds reasonable to me. > > > As I've been going along I've added feature flags for SSE4a and > SSE5. These > really do need to be separate feature flags because having SSE4a and/ > or SSE5 > does not imply that you have SSE4.2 or SSE4.1. So th...

...one > of the function what is the subtarget feature by calling few routines of > Subtarget. > > > > Subtarget->hasMMX() ------ true > > Subtarget->hasSSE1() ------ true > > Subtarget->hasSSE2() ------ true > > > > These functions just compare the X86SSELevel with subtarget enum values > like MMX, SSE1, SSE2 etc. > > > > hasMMX() { return X86SSELevel >= MMX}; // similar for others > > > > Now, enum values start from MMX and goes on increasing with SSE1, SSE2, > etc. > > > > For the above test case, the X86SS...

...; As I've been going along I've added feature flags for SSE4a and >> SSE5. These >> really do need to be separate feature flags because having SSE4a and/ >> or SSE5 >> does not imply that you have SSE4.2 or SSE4.1. So they can't be >> part of the >> X86SSELevel scheme. >> [...] > > Offhand, I'd say SSE4a and SSE5 ought to be separate flags too. FWIW we added a flag for SSE4A in a commit yesterday, as well as more AMD architecture types. -- Stefanus Du Toit <stefanus.dutoit at rapidmind.com> RapidMind Inc. phone: +1 519 885...

...enning, > > I believe the code that is supposed to do this is in: > lib/Target/X86/X86Subtarget.cpp in > X86Subtarget::AutoDetectSubtargetFeatures() > Is there a bug in that function? I read there: // FIXME: AVX codegen support is not ready. //if ((ECX >> 28) & 1) { X86SSELevel = AVX; ToggleFeature(X86::FeatureAVX); } It looks like the check for AVX is disabled intentionally. But if the AVX codegen is now usable, one could enable the AVX check, right?

Henning, I believe the code that is supposed to do this is in: lib/Target/X86/X86Subtarget.cpp in X86Subtarget::AutoDetectSubtargetFeatures() Is there a bug in that function? -Hal On Thu, 24 May 2012 23:56:48 +0200 (CEST) Henning Thielemann <llvm at henning-thielemann.de> wrote: > > On Thu, 24 May 2012, Pan, Wei wrote: > > > Very likely AVX is not enabled in your llc.

...3452816845 unsigned int BytesToPopOnReturn 0 int BytesCallerReserves 0 int - Subtarget 0x00000000008eda90 {AsmFlavor=Intel PICStyle=None X86SSELevel=SSE2 ...} const llvm::X86Subtarget * + llvm::TargetSubtarget {...} llvm::TargetSubtarget AsmFlavor Intel llvm::X86Subtarget::AsmWriterFlavorTy PICStyle None...

...t is supposed to do this is in: > > lib/Target/X86/X86Subtarget.cpp in > > X86Subtarget::AutoDetectSubtargetFeatures() > > Is there a bug in that function? > > I read there: > > // FIXME: AVX codegen support is not ready. > //if ((ECX >> 28) & 1) { X86SSELevel = AVX; > ToggleFeature(X86::FeatureAVX); } > > > It looks like the check for AVX is disabled intentionally. > But if the AVX codegen is now usable, one could enable the AVX check, > right? -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National L...

On Feb 12, 2008, at 5:26 PM, Chuck Rose III wrote: > Hola LLVMers, > > I’m debugging through some strangeness that I’m seeing on X64 on > windows with LLVM2.2. I had to change the code so that it would > engage the x64 target machine on windows builds, but I’ve otherwise > left LLVM 2.2 alone. The basic idea is that I’ve got a function bar > which is compiled by

Hola LLVMers, I'm debugging through some strangeness that I'm seeing on X64 on windows with LLVM2.2. I had to change the code so that it would engage the x64 target machine on windows builds, but I've otherwise left LLVM 2.2 alone. The basic idea is that I've got a function bar which is compiled by VStudio and I'm creating another function foo via LLVM JIT which is going