Displaying 3 results from an estimated 3 matches for "x86smul_flag".
2020 May 12
2
BPF tablegen+codegen question
.... src1 and src2 are GR64
registers.
def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
(ins GR64:$src1, GR64:$src2),
"imul{q}\t{$src2, $dst|$dst, $src2}",
[(set GR64:$dst, EFLAGS,
(X86smul_flag GR64:$src1, GR64:$src2))]>,
Sched<[WriteIMul64Reg]>, TB;
Chris
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2018 Nov 14
2
Fw: How to define an instruction
...is the definition of IMUL32rr in X86InstrArithmetic.td. "WriteIMul32Reg" is the most important and the defines the multiplication.
def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),"imul{l}\t{$src2, $dst|$dst, $src2}", [(set GR32:$dst, EFLAGS, (X86smul_flag GR32:$src1, GR32:$src2))]>,Sched<[WriteIMul32Reg]>, TB, OpSize32;
And in X86ScheduleXXX.td ,there is definition of Ports and so on.
My questions are here,as following:
1.whether the schedule of an instruction defines the machine how to do.
2.Why is there no "add" or "sub&q...
2018 Nov 14
2
Fw: How to define an instruction
...is the definition of IMUL32rr in X86InstrArithmetic.td. "WriteIMul32Reg" is the most important and the defines the multiplication.
def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),"imul{l}\t{$src2, $dst|$dst, $src2}", [(set GR32:$dst, EFLAGS, (X86smul_flag GR32:$src1, GR32:$src2))]>,Sched<[WriteIMul32Reg]>, TB, OpSize32;
And in X86ScheduleXXX.td ,there is definition of Ports and so on.
My questions are here,as following:
1.whether the schedule of an instruction defines the machine how to do.
2.Why is there no "add" or "sub&q...