search for: x86selectiondaginfo

On Tue, Jul 30, 2013 at 01:14:16PM -0600, Dan wrote: > I'll try to run through the scenario: > > > 64-bit register type target (all registers have 64 bits). > > all 32-bits are getting promoted to 64-bit integers > > Problem: > > MUL on i32 is getting promoted to MUL on i64 > > MUL on i64 is getting expanded to a library call in compiler-rt > >

...alization. Right now, type legalization, promotes all MUL I32 to 64-bit, and I lose the ability to differentiate between what originally was a MUL on 64-bit and 32-bit values. Only thing that I have seen happen at DAG Selection is for lowering custom intrinsic functions like memcpy: ./Target/X86/X86SelectionDAGInfo.cpp:178:X86SelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, Is there a general SelectionDAG conversion that can be made to happen before all type promotions? Again, even modifications in ISelDAGToDAG.cpp will be after type promotion in my understanding. On Tue, Jul 30, 2013 a...

I'll try to run through the scenario: 64-bit register type target (all registers have 64 bits). all 32-bits are getting promoted to 64-bit integers Problem: MUL on i32 is getting promoted to MUL on i64 MUL on i64 is getting expanded to a library call in compiler-rt the problem is that MUL32 gets promoted and then converted into a subroutine call because it is now type i64, even though

On Wed, Mar 16, 2016 at 11:48 AM, Mehdi Amini <mehdi.amini at apple.com> wrote: > Hi Rail, > > Two hints to begin with: > > 1) Makes sure you example is vectorized on X86 for example > 2) Is your target correctly overriding the TTI (declaring the vector > register size for example) so that the vectorizer can kicks-in (see > X86TTIImpl::getRegisterBitWidth for

...t; You need to express how to legalize/select the BUILD_VECTOR in > SelectionDAG to instructions that your target supports. You can look at > what other targets are doing. > > -- > Mehdi > > Thanks for the reply. Do you mind pointing out the files I need to look at? I looked at X86SelectionDAGInfo.cpp as well as ARMSelectionDAGInfo.cpp but couldn't find anything relevant. -- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160317/65440088/atta...

...39;/home/NIKHILREDDY/WORK/LLVM_OBJ/lib/Analysis' make[3]: Entering directory '/home/NIKHILREDDY/WORK/LLVM_OBJ/lib/Transforms/InstCombine' llvm[3]: Compiling InstCombineAddSub.cpp for Release+Asserts build llvm[3]: Compiling LoopRerollPass.cpp for Release+Asserts build llvm[3]: Compiling X86SelectionDAGInfo.cpp for Release+Asserts build llvm[3]: Compiling DwarfCFIException.cpp for Release+Asserts build llvm[3]: Compiling InstCombineAndOrXor.cpp for Release+Asserts build llvm[3]: Compiling X86Subtarget.cpp for Release+Asserts build llvm[3]: Compiling LoopRotation.cpp for Release+Asserts build llvm[3]:...