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Inspired by https://www.agner.org/optimize/instruction_tables.pdf, which gives us the latency and reciprocal throughput of each instruction in the different architecture of X86, Is there anybody taking the effort to do a similar job for LLVM IR? Thanks! -------------- next part -------------- An HTML attachment was scrubbed... URL:

...op support for the old itinerary format and postRA scheduler as soon as possible. > > To give you an example, the new model would look something like this: > > def : WriteRes<WriteShift, [IEC_RSV0]> { let Latency = 2; } > > Maybe a new WriteShiftCL type should be added to X86Schedule.td and referenced in X86InstrShiftRotate.td. Then SLM can define it with Latency = 4, and X86SchedSandyBridge.td can have: > > def : SchedAlias<WriteShiftCL, WriteShift>; > > It's also possible for a subtarget to override specific operations by pattern matching opcodes witho...