search for: x86memoperand

What does MIOperandInfo exactly mean while defining an Operand class? e.g. here class X86MemOperand<string printMethod> : Operand<iPTR> { let PrintMethod = printMethod; let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm); } -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20071204/23db1ace/...

...tching in target files. Some of them seem intuitive. But I want to get it clarified anyway. I am using a pattern from X86InstrFMA.td in the below example. Consider FMA3 pattern (simplified). let Constraints = "$src1 = $dst" in { multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop, RegisterClass RC, ValueType OpVT, PatFrag mem_frag, SDPatternOperator OpNode = null_frag> { def r : FMA3<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2, RC:$src3), !strconcat(OpcodeStr,...

On Tue, Jun 24, 2014 at 4:03 PM, Tim Northover <t.p.northover at gmail.com> wrote: > Hi Jun, > > On 24 June 2014 08:08, Jun Koi <junkoi2004 at gmail.com> wrote: > > def LEA16r : I<0x8D, MRMSrcMem, > > (outs GR16:$dst), (ins i32mem:$src), > > "lea{w}\t{$src|$dst}, {$dst|$src}", [], IIC_LEA_16>, > >

...o implementations to define the instruction in TableGen *.td file? (1) Similar to what has been done to complex X86 addressing mode. A single 32-bit immediate (i32) encodes how to add many MachineOperands to the MachineInstr object (With the help of functions in X86InstrBuilder.h). // similar to X86MemOperand in X86InstrInfo.td !! class ManyOperands : Operand<i32> { let NumMIOperands = 100; // a very large number let PrintMethod = "printManyOperands"; } def MO : ManyOperands; def FOOBAR: Instruction<(ops MO:$operands), "foobar {$operands}">; (2) 'Collapse'...

...of them seem intuitive. But I > want to get it clarified anyway. I am using a pattern from > X86InstrFMA.td in the below example. Consider FMA3 pattern > (simplified). > > let Constraints = "$src1 = $dst" in { > multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop, > RegisterClass RC, ValueType OpVT, PatFrag mem_frag, > SDPatternOperator OpNode = null_frag> { > > def r : FMA3<opc, MRMSrcReg, (outs RC:$dst), > (ins RC:$src1, RC:$src2, RC:$src3), >...

...in the range [0, 31]), but i cannot find this TYPE_IMM5 > value anywhere in the definition of CMPSS, as below. > can somebody please enlighten me? > > thanks! > > // sse12_cmp_packed - sse 1 & 2 compare packed instructions > multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop, > Operand CC, Intrinsic Int, string asm, > string asm_alt, Domain d, > OpndItins itins = SSE_ALU_F32P> { > def rri : PIi8<0xC2, MRMSrcReg, > (outs RC:$dst), (ins RC:$src...

hi, some instructions mismatch between assembler & disassembler, like below. it seems this happens with all SSECC related instructions? thanks, Jun $ echo "cmpps xmm1, xmm2, 23" | ./Release+Asserts/bin/llvm-mc -assemble -triple=x86_64 --output-asm-variant=1 -x86-asm-syntax=intel -show-encoding .text cmpps xmm1, xmm2, 23 # encoding: [0x0f,0xc2,0xca,0x17] $

...$wsi a memory operand (otherwise we get the difficult error: <<In LD_INDIRECT_D2: Type inference contradiction found, 'v128i16' needs to be scalar>>), like in the following complete specification: // Inspired heavily from lib/Target/X86/X86InstrInfo.td class X86MemOperand<string printMethod> : Operand<iPTR> { let PrintMethod = printMethod; let MIOperandInfo = (ops i8imm, i32imm); let OperandType = "OPERAND_MEMORY"; } // Gather mem operands class X86VMemOperand<RegisterClass RC, stri...

...into isAsmParserOnly = 1 block so that existing VCVTSI2SD definition takes effect only in asm parser. Example solution is as follows. lib/Target/X86/x86InstrSSE.td ... multiclass sse12_vcvt_avx_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC, SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag, string asm> { def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm, [(set DstRC:$dst, (OpNode SrcRC:$src))]>; def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,...

On Wed, Nov 7, 2012 at 10:52 PM, Anitha Boyapati <anitha.boyapati at gmail.com>wrote: ... > For the multiclass "fma4s", why is "mr" not inherited from "VEX_W" and > "MemOp4" like those of "rm" or "rr" ? > Hey Anitha, The VEX.W bit is used to denote operand order. In other words, this bit allows for a memop to be used as

...> > want to get it clarified anyway. I am using a pattern from > > X86InstrFMA.td in the below example. Consider FMA3 pattern > > (simplified). > > > > let Constraints = "$src1 = $dst" in { > > multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand > x86memop, > > RegisterClass RC, ValueType OpVT, PatFrag mem_frag, > > SDPatternOperator OpNode = null_frag> { > > > > def r : FMA3<opc, MRMSrcReg, (outs RC:$dst), > > (ins RC:$src1, RC:$src2, R...

...perand (otherwise we get the > difficult error: <<In LD_INDIRECT_D2: Type inference contradiction found, 'v128i16' needs > to be scalar>>), like in the following complete specification: > // Inspired heavily from lib/Target/X86/X86InstrInfo.td > class X86MemOperand<string printMethod> : Operand<iPTR> { > let PrintMethod = printMethod; > let MIOperandInfo = (ops i8imm, i32imm); > let OperandType = "OPERAND_MEMORY"; > } > // Gather mem operands > class X86VMemOperand&l...

Hi, A question from r162999 changes: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFMA.td?r1=162999&r2=162998&pathrev=162999 For the multiclass "fma4s", why is "mr" not inherited from "VEX_W" and "MemOp4" like those of "rm" or "rr" ? multiclass fma4s< > ... def mr : FMA4<opc, MRMSrcMem, (outs

Hello. Will, thanks a lot for pointing me to the MaskedGatherSDNode and mgatherv4i32. I have to say that the definition of the "multiclass avx512_gather" from lib/Target/X86/X86InstrAVX512.td is difficult to follow and I prefer not to use it. I currently have some serious problems with TableGen - it gives an assertion failure:

Hi Tim, I'm sorry to bother you again. Since I have met the problem, how to check used registers and avoid clobbering live registers, which you mentioned in the email. I am working in the function X86InstrInfo::storeRegToStackSlot, which is in lib/Target/X86/X86InstrInfo.cpp. And I have an extra problem, may I use MOV64mr and two addReg to set two registers as its arguments? I want to use

...numerated value. [2]. How does vex_w help in instruction selection in-addition to FMA4 class? [3]. Why does only "rr" and "rm" forms have vex_w but not "mr" ? (Reference) multiclass fma4s<bits<8> opc, string OpcodeStr, RegisterClass RC, X86MemOperand x86memop, ValueType OpVT, SDNode OpNode, PatFrag mem_frag> { def rr : FMA4<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2, RC:$src3), !strconcat(OpcodeStr, "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),...

Thanks for your help! I'm much more clear about this problem. Will 2018-04-13 17:53 GMT+08:00 Tim Northover <t.p.northover at gmail.com>: > Hi Will, > > On 13 April 2018 at 09:50, Will Lester via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > > I have used BuildMI to build a MachineInstr. But it seems that a call > > MachineInstr only has one parameter

...per <craig.topper at gmail.com> wrote: > masked_gather returns two results. The data and the modified mask. Note > the $dst and the $mask_wb in the pattern below. > > multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _, > X86MemOperand memop, PatFrag GatherNode> { > let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb", > ExeDomain = _.ExeDomain in > def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb), > (ins _.RC:$src1, _.KRCWM:$mask, memop:$src...

...The data and the modified mask. >>>>> Note the $dst and the $mask_wb in the pattern below. >>>>> >>>>> multiclass avx512_gather<bits<8> opc, string OpcodeStr, >>>>> X86VectorVTInfo _, >>>>> X86MemOperand memop, PatFrag GatherNode> { >>>>> let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = >>>>> $mask_wb", >>>>> ExeDomain = _.ExeDomain in >>>>> def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, >>&...

i want to implement gather for v64i32. i wrote following code. def GATHER_256B : I<0x68, MRMSrcMem, (outs VR_2048:$dst), (ins i2048mem:$src), "GATHER_256B\t{$src, $dst|$dst, $src}", [(set VR_2048:$dst, (v64i32 (masked_gather addr:$src)))], IIC_MOV_MEM>, TA; def: Pat<(v64f32 (masked_gather addr:$src)), (GATHER_256B