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Just a heads up that the llvm build appears to be broken on cygwin. I haven't investigated, but here's the failures: llvm[3]: Compiling X86ISelDAGToDAG.cpp for Release+Asserts build /home/Eric/boost/consulting/svn/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1487: error: ‘LOCK_OR8mi’ is not a member of ‘llvm::X86’ /home/Eric/boost/consulting/svn/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1488: error: ‘LOCK_OR8mr’ is not a member of ‘llvm::X86’ /home/Eric/...

On May 14, 2011, at 3:08 AM, Eric Niebler wrote: > Just a heads up that the llvm build appears to be broken on cygwin. I > haven't investigated, but here's the failures: > > llvm[3]: Compiling X86ISelDAGToDAG.cpp for Release+Asserts build > /home/Eric/boost/consulting/svn/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1487: > error: ‘LOCK_OR8mi’ is not a member of ‘llvm::X86’ > /home/Eric/boost/consulting/svn/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1488: > error: ‘LOCK_OR8mr’ is not a member of ‘ll...

On 5/17/2011 2:58 AM, Eric Christopher wrote: > On May 14, 2011, at 3:08 AM, Eric Niebler wrote: > >> Just a heads up that the llvm build appears to be broken on cygwin. I >> haven't investigated, but here's the failures: >> >> llvm[3]: Compiling X86ISelDAGToDAG.cpp for Release+Asserts build >> /home/Eric/boost/consulting/svn/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1487: >> error: ‘LOCK_OR8mi’ is not a member of ‘llvm::X86’ >> /home/Eric/boost/consulting/svn/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1488: >> error: ‘LOCK_OR8mr’ is not...

...1 2:58 AM, Eric Christopher wrote: >> On May 14, 2011, at 3:08 AM, Eric Niebler wrote: >> >>> Just a heads up that the llvm build appears to be broken on cygwin. I >>> haven't investigated, but here's the failures: >>> >>> llvm[3]: Compiling X86ISelDAGToDAG.cpp for Release+Asserts build >>> /home/Eric/boost/consulting/svn/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1487: >>> error: ‘LOCK_OR8mi’ is not a member of ‘llvm::X86’ >>> /home/Eric/boost/consulting/svn/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1488: >>> error: ‘LO...

On 5/18/2011 1:47 AM, Eric Christopher wrote: > On May 17, 2011, at 2:50 AM, Eric Niebler wrote: >> On 5/17/2011 2:58 AM, Eric Christopher wrote: >>> On May 14, 2011, at 3:08 AM, Eric Niebler wrote: >>> >>>> Just a heads up that the llvm build appears to be broken on cygwin. I >>>> haven't investigated, but here's the failures:

...llvm::SDOperand) (this=0x822d660, Result=@0xbf800a10, N={Val = 0x8254338, ResNo = 0}) at X86GenDAGISel.inc:27833 #2 0x40ada64f in (anonymous namespace)::X86DAGToDAGISel::Select(llvm::SDOperand&, llvm::SDOperand) (this=0x822d660, Result=@0xbf800a10, N={Val = 0x8254338, ResNo = 0}) at X86ISelDAGToDAG.cpp:835 #3 0x40b00bb4 in (anonymous namespace)::X86DAGToDAGISel::SelectCode(llvm::SDOperand&, llvm::SDOperand) (this=0x822d660, Result=@0xbf800d28, N={Val = 0x8254458, ResNo = 0}) at X86GenDAGISel.inc:27686 #4 0x40ada64f in (anonymous namespace)::X86DAGToDAGISel::Select(llvm::SDOperand&a...

...V with code containing control flow to select between the intended IDIV/DIV and an 8-bit DIV with movzx, as described in the Intel Atom Optimization Guide. My first attempt was to add this with a custom inserter in X86ISelLowering (see EmitInstrWithCustomInserter). However, the isel already done in X86ISelDAGToDAG, line 2200, adds multiple instructions which makes adding control flow in X86ISelLowering difficult. Also, it looks like control flow cannot be added in X86ISelDAGToDAG. Any suggestions are appreciated. Thanks, Tyler Nowicki Intel -------------- next part -------------- An HTML attachment was sc...

...VisitedSDNodeSet once; - DumpNodesr(errs(), this, 0, 0, once); + DumpNodesr(dbgs(), this, 0, 0, once); } void SDNode::dumpr(const SelectionDAG *G) const { VisitedSDNodeSet once; - DumpNodesr(errs(), this, 0, G, once); + DumpNodesr(dbgs(), this, 0, G, once); } Index: lib/Target/X86/X86ISelDAGToDAG.cpp =================================================================== --- lib/Target/X86/X86ISelDAGToDAG.cpp (revision 91557) +++ lib/Target/X86/X86ISelDAGToDAG.cpp (working copy) @@ -116,37 +116,37 @@ } void dump() { - errs() << "X86ISelAddressMode " << thi...

...llvm::SDOperand) (this=0x822d660, Result=@0xbf800a10, N={Val = 0x8254338, ResNo = 0}) at X86GenDAGISel.inc:27833 #2 0x40ada64f in (anonymous namespace)::X86DAGToDAGISel::Select(llvm::SDOperand&, llvm::SDOperand) (this=0x822d660, Result=@0xbf800a10, N={Val = 0x8254338, ResNo = 0}) at X86ISelDAGToDAG.cpp:835 #3 0x40b00bb4 in (anonymous namespace)::X86DAGToDAGISel::SelectCode(llvm::SDOperand&, llvm::SDOperand) (this=0x822d660, Result=@0xbf800d28, N={Val = 0x8254458, ResNo = 0}) at X86GenDAGISel.inc:27686 #4 0x40ada64f in (anonymous namespace)::X86DAGToDAGISel::Select(llvm::SDOperand&a...

...his=0x42025600, DAG=@0xbfffe47c) at /Volumes/Gir/devel/llvm/ llvm.src/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:4847 #12 0x0067fcca in (anonymous namespace)::X86DAGToDAGISel::InstructionSelectBasicBlock (this=0x42025600, DAG=@0xbfffe47c) at /Volumes/Gir/devel/llvm/ llvm.src/lib/Target/X86/X86ISelDAGToDAG.cpp:483 #13 0x007f80cc in llvm::SelectionDAGISel::CodeGenAndEmitDAG (this=0x42025600, DAG=@0xbfffe47c) at /Volumes/Gir/devel/llvm/ llvm.src/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:4623 #14 0x0080bd86 in llvm::SelectionDAGISel::SelectBasicBlock (this=0x42025600, LLVMBB=0x41a22080, MF=@0x4...

Hi Ankur, > The flags "-view-sched-dags".. described in the doc doesn't seem to work. ( > "llc -help" doesn't list it ). as far as I remember, displaying DAGs during compilation is only enabled in "debug builds" [1] of LLVM. You probably have to re-configure and re-compile LLVM to enable this feature. Best regards, Christoph [1]

...> Result=@0xbf800a10, N={Val = 0x8254338, ResNo = 0}) at > X86GenDAGISel.inc:27833 > #2 0x40ada64f in (anonymous namespace)::X86DAGToDAGISel::Select > (llvm::SDOperand&, llvm::SDOperand) (this=0x822d660, > Result=@0xbf800a10, N={Val = 0x8254338, ResNo = 0}) at > X86ISelDAGToDAG.cpp:835 > #3 0x40b00bb4 in (anonymous namespace)::X86DAGToDAGISel::SelectCode > (llvm::SDOperand&, llvm::SDOperand) (this=0x822d660, > Result=@0xbf800d28, N={Val = 0x8254458, ResNo = 0}) at > X86GenDAGISel.inc:27686 > #4 0x40ada64f in (anonymous namespace)::X86DAGToDAGIS...

...match, we then know it needs manual lowering and selection. >> legalize >> | >> V >> manual lowering (X86ISelLowering) >> | >> V >> manual isel (X86ISelDAGToDAG) >> | >> V >> table-driven isel (.td files/X86GenDAGISel) >> | >> V >> manual isel (some to-be-design piece) > > I'm not sure what you mean here. Are you suggestin...

I am trying to understand the SelectionDAG construction from LLVM IR. I have gone through the doc "The LLVM Target-Independent Code Generator" on LLVM site. This gives a great initial overview. However I am unable to catch the actual control flow for the llvm->selectionDag conversion. The flags "-view-sched-dags".. described in the doc doesn't seem to work. ( "llc

...ome output goes out > early and the rest gets dumped at the end. > > Please review and let me know if the general approach is ok. I will > start to convert files once I get the ok. Sounds good. > +++ lib/CodeGen/SelectionDAG/SelectionDAG.cpp (working copy) > +++ lib/Target/X86/X86ISelDAGToDAG.cpp (working copy) Looks fine to me, go ahead and convert stuff over when the dependencies go in. Please make sure not to change things that *really should* go errs(), such as stuff in top level tools that want to print errors. -Chris

Hi Tyler, > -Does anyone know where a backend-specific optimization can be added to replace > an instruction with code containing control flow? I think the backend lowering of atomic intrinsics generates control flow (loops), so that may give you a clue. Ciao, Duncan.

...do some cleanup before the main table-driven > isel. > > Obviously a lot of details have to be worked out. I'm not seeing how this is useful for shuffles. Since tblgen doesn't generate table based matching for *any* shuffles, all of the matching code would end up as C++ code in X86ISelDagToDag, which would give us all of the problems we had before by moving to X86ISD nodes. >>> 2. Sometimes DAGs are legal in some contexts but not others and it is a >>> pain to deal with. A good example is VBROADCAST, where a <0,0,0,0> >>> shuffle is natively supported...

...s and a lot of other manual checks if we just had another isel phase. Let's say we structured things this way: legalize | V manual lowering (X86ISelLowering) | V manual isel (X86ISelDAGToDAG) | V table-driven isel (.td files/X86GenDAGISel) | V manual isel (some to-be-design piece) The idea is that we keep the existing manual pieces where they are to clean things up for TableGen-based isel and...

...we > just had another isel phase. Let's say we structured things this way: > > legalize > | > V > manual lowering (X86ISelLowering) > | > V > manual isel (X86ISelDAGToDAG) > | > V > table-driven isel (.td files/X86GenDAGISel) > | > V > manual isel (some to-be-design piece) > > The idea is that we keep the existing manual pieces where they are to > clea...

Hi Bruce, Thanks for you reply. I check the *.td files under the lib/Target/X86 folder, but have not got interesting findings. It requires some knowledge of LLVM backend to fully understand the *.td files. I will get some background and keep searching. Of course I appreciate if anyone with such experience can point the concrete locations. Regards, Hu Hong On 17 October 2016 at 22:20, Bruce