search for: x86fastisel

Hi All, I want to use Fast Instruction Selection for my X86 back-end. However, my code often uses these two intrinsic functions: x86_sse_movmsk_ps and x86_sse2_pcmpeq_d, which are not supported yet by X86FastISel. Could you guys please show me how to add support for this two Intrinsics? Pointing out one example would be great, I can follow to implement others. I just know that I need to modify X86FastISel::X86VisitIntrinsicCall(const IntrinsicInst &), but not sure what needed here :). Thank you in ad...

In X86FastISel::X86SelectStore(), improperly aligned stores are rejected and handled by the DAG-based ISel. However, X86FastISel::X86SelectLoad() makes no such requirement. Is there a reason for this alignment restriction on stores? Would it be reasonable to remove it? Jim -------------- next part -----------...

...ong int, llvm::MachineInstr*, llvm::MachineInstr&>> = {<No data fields>}, NodePtr = 0x4b69388}, DL={LineCol = 0, ScopeIdx = 0}, TID=@0x803a99240) at MachineInstrBuilder.h:183 #3 0x00000008033c7637 in X86SelectRet (this=0x4530bd0, I=0x493fae0) at /tmp/llvm-svn/llvm/lib/Target/X86/X86FastISel.cpp:771 #4 0x00000008033cc4fc in TargetSelectInstruction (this=0x4530bd0, I=0x493fae0) at /tmp/llvm-svn/llvm/lib/Target/X86/X86FastISel.cpp:1783 #5 0x000000080315a64f in llvm::FastISel::SelectInstruction (this=0x4530bd0, I=0x493fae0) at /tmp/llvm-svn/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp:...

On Aug 27, 2010, at 11:00 AMPDT, Eric Christopher wrote: >>> >>> For some reason I am getting this error even when I only have an >>> empty 'main' function. So I couldn't create .ll file reproducing >>> it and I have to debug myself. >>> >>> The function causing the problem is stub created in >>> JIT::runFunction:

...sage: https://llvm.org/bugs/show_bug.cgi?id=23203 Report of rust bug: https://github.com/rust-lang/rust/issues/26449 Discussion on why Rust doesn't want to fix (a refused patch to libcore): https://github.com/rust-lang/rust/pull/26749 The error is coming from one of these files: lib/Target/X86/X86FastISel.cpp:3166: report_fatal_error("SSE register return with SSE disabled"); lib/Target/X86/X86ISelLowering.cpp:2107: report_fatal_error("SSE register return with SSE disabled"); lib/Target/X86/X86ISelLowering.cpp:2261: report_fatal_error("SSE register return with...

...hineInstr*, llvm::MachineInstr&>> = {<No data > fields>}, NodePtr = 0x4b69388}, DL={LineCol = 0, ScopeIdx = 0}, > TID=@0x803a99240) at MachineInstrBuilder.h:183 > #3 0x00000008033c7637 in X86SelectRet (this=0x4530bd0, I=0x493fae0) at > /tmp/llvm-svn/llvm/lib/Target/X86/X86FastISel.cpp:771 > #4 0x00000008033cc4fc in TargetSelectInstruction (this=0x4530bd0, > I=0x493fae0) at /tmp/llvm-svn/llvm/lib/Target/X86/X86FastISel.cpp:1783 > #5 0x000000080315a64f in llvm::FastISel::SelectInstruction > (this=0x4530bd0, I=0x493fae0) at > /tmp/llvm-svn/llvm/lib/CodeGen/Sele...

On Aug 27, 2010, at 11:53 AMPDT, Yuri wrote: > On 08/27/2010 11:32, Yuri wrote: >> As I understand only one of TCRETURNri64 and RET should be created. >> I have sources of rev.112200. >> >> Here is the stack when TCRETURNri64 instruction is created: >> #1 0x0000000802c8b4e2 in llvm::MachineFunction::CreateMachineInstr >> (this=0x30eb000, TID=@0x803a78940,

...ong int, llvm::MachineInstr*, llvm::MachineInstr&>> = {<No data fields>}, NodePtr = 0x4b69388}, DL={LineCol = 0, ScopeIdx = 0}, TID=@0x803a99240) at MachineInstrBuilder.h:183 #3 0x00000008033c7637 in X86SelectRet (this=0x4530f30, I=0x493f240) at /tmp/llvm-svn/llvm/lib/Target/X86/X86FastISel.cpp:771 #4 0x00000008033cc4fc in TargetSelectInstruction (this=0x4530f30, I=0x493f240) at /tmp/llvm-svn/llvm/lib/Target/X86/X86FastISel.cpp:1783 #5 0x000000080315a64f in llvm::FastISel::SelectInstruction (this=0x4530f30, I=0x493f240) at /tmp/llvm-svn/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp:...

...) Need actual calling convention Touches: - include/llvm/CallingConv.h - lib/Target/X86/X86CallingConv.td 2) Handling new calling convention (including allowing it to be used in tail call optimisation). Touches: - lib/Target/X86/X86ISelLowering.cpp - lib/Target/X86/X86FastISel.cpp 3) New calling convention needs different callee save register list. Touches: - lib/Target/X86/X86RegisterInfo.cpp The GHC developers would love to get this included in LLVM so that we don't need to carry around our own version of LLVM. If this patch isn't something that yo...

Hi everyone, I found that LLVM generates redundant code when calling functions with constant parameters, with optimizations disabled. Consider the following C code snippet: int foo(int x, int y); void bar() { foo(1, 2); foo(3, 4); } Clang/LLVM 6.0 generates the following assembly code: _bar: subl $32, %esp movl $1, %eax movl $2, %ecx movl $1, (%esp) movl $2, 4(%esp) movl %eax, 28(%esp) movl

Sorry I missed that important detail. The relevant part of the command line is: -cc1 -S -triple i386-pc-win32 I don't expect it matters if it's for Windows or Linux in this case. On Fri, Sep 14, 2018 at 9:16 PM David Blaikie <dblaikie at gmail.com> wrote: > Can't say I've observed that behavior (though I'm just building from > top-of-tree rather than 6.0,

...onLoweringInfo.cpp | 2 +- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 4 ++-- lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 2 +- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 20 ++++++++++---------- lib/CodeGen/SelectionDAG/TargetLowering.cpp | 8 ++++---- lib/Target/X86/X86FastISel.cpp | 4 ++-- 7 files changed, 24 insertions(+), 24 deletions(-) commit 9f0cb7ed22f2791a7f315d44827a64de2503e145 Author: Patrik Hägglund <patrik.h.hagglund at ericsson.com> Date: Wed Dec 5 14:04:17 2012 +0100 Change a parameter of TargetLowering::getVectorTypeBreakd...

...lvm/trunk/lib/IR/AutoUpgrade.cpp > llvm/trunk/lib/IR/IRBuilder.cpp > llvm/trunk/lib/IR/Verifier.cpp > llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp > llvm/trunk/lib/Target/ARM/ARMFastISel.cpp > llvm/trunk/lib/Target/Mips/MipsFastISel.cpp > llvm/trunk/lib/Target/X86/X86FastISel.cpp > llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp > llvm/trunk/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp > llvm/trunk/test/Analysis/AliasSet/memtransfer.ll > llvm/trunk/test/Analysis/BasicAA/assume.ll > llvm/trunk/test/Analysis/BasicAA/cs-cs.ll &gt...

...AG/SelectionDAGBuilder.cpp llvm/trunk/lib/IR/AutoUpgrade.cpp llvm/trunk/lib/IR/IRBuilder.cpp llvm/trunk/lib/IR/Verifier.cpp llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp llvm/trunk/lib/Target/ARM/ARMFastISel.cpp llvm/trunk/lib/Target/Mips/MipsFastISel.cpp llvm/trunk/lib/Target/X86/X86FastISel.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp llvm/trunk/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp llvm/trunk/test/Analysis/AliasSet/memtransfer.ll llvm/trunk/test/Analysis/BasicAA/assume.ll llvm/trunk/test/Analysis/BasicAA/cs-cs.ll llvm/trunk/test/Analysis/B...

...rade.cpp >> llvm/trunk/lib/IR/IRBuilder.cpp >> llvm/trunk/lib/IR/Verifier.cpp >> llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp >> llvm/trunk/lib/Target/ARM/ARMFastISel.cpp >> llvm/trunk/lib/Target/Mips/MipsFastISel.cpp >> llvm/trunk/lib/Target/X86/X86FastISel.cpp >> llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp >> llvm/trunk/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp >> llvm/trunk/test/Analysis/AliasSet/memtransfer.ll >> llvm/trunk/test/Analysis/BasicAA/assume.ll >> llvm/trunk/test/Analysis/...

...ldPrint = true; } - return ShouldPrint; } Index: lib/Target/X86/CMakeLists.txt =================================================================== --- lib/Target/X86/CMakeLists.txt (revision 196508) +++ lib/Target/X86/CMakeLists.txt (working copy) @@ -18,6 +18,7 @@ X86CodeEmitter.cpp X86FastISel.cpp X86FloatingPoint.cpp + X86FoldRedundantInserts.cpp X86FrameLowering.cpp X86ISelDAGToDAG.cpp X86ISelLowering.cpp Index: lib/Target/X86/X86FoldRedundantInserts.cpp =================================================================== --- lib/Target/X86/X86FoldRedundantInserts.cpp (revi...

...llvm/trunk/lib/IR/IRBuilder.cpp >>> llvm/trunk/lib/IR/Verifier.cpp >>> llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp >>> llvm/trunk/lib/Target/ARM/ARMFastISel.cpp >>> llvm/trunk/lib/Target/Mips/MipsFastISel.cpp >>> llvm/trunk/lib/Target/X86/X86FastISel.cpp >>> llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp >>> llvm/trunk/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp >>> llvm/trunk/test/Analysis/AliasSet/memtransfer.ll >>> llvm/trunk/test/Analysis/BasicAA/assume.ll >>> llvm/...

...AG/SelectionDAGBuilder.cpp llvm/trunk/lib/IR/AutoUpgrade.cpp llvm/trunk/lib/IR/IRBuilder.cpp llvm/trunk/lib/IR/Verifier.cpp llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp llvm/trunk/lib/Target/ARM/ARMFastISel.cpp llvm/trunk/lib/Target/Mips/MipsFastISel.cpp llvm/trunk/lib/Target/X86/X86FastISel.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp llvm/trunk/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp llvm/trunk/test/Analysis/AliasSet/memtransfer.ll llvm/trunk/test/Analysis/BasicAA/assume.ll llvm/trunk/test/Analysis/BasicAA/cs-cs.ll llvm/trunk/test/Analysis/B...

Hi all, There's been a recent bootstrap failure that might be covered up because of another failure. I just wanted to point this out so that people can take a look: -bw Here's the failure from our buildbot: Assertion failed: (DestReg == VirtReg && "Unknown load situation!"), function RewriteMBB, file /Volumes/Sandbox/Buildbot/llvm/build.llvm-

...AG/SelectionDAGBuilder.cpp llvm/trunk/lib/IR/AutoUpgrade.cpp llvm/trunk/lib/IR/IRBuilder.cpp llvm/trunk/lib/IR/Verifier.cpp llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp llvm/trunk/lib/Target/ARM/ARMFastISel.cpp llvm/trunk/lib/Target/Mips/MipsFastISel.cpp llvm/trunk/lib/Target/X86/X86FastISel.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp llvm/trunk/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp llvm/trunk/test/Analysis/AliasSet/memtransfer.ll llvm/trunk/test/Analysis/BasicAA/assume.ll llvm/trunk/test/Analysis/BasicAA/cs-cs.ll llvm/trunk/test/Analysis/B...