Displaying 2 results from an estimated 2 matches for "x86expandatomicpass".
2014 Aug 08
6
[LLVMdev] Plan to optimize atomics in LLVM
> I am planning in doing in IR, but with target specific-passes (such as X86ExpandAtomicPass)
> that just share some of the code
This would more normally be done via target hooks in LLVM, though the
principle is sound.
> But it must be target-dependent as for example on Power a
> seq_cst store has a fence before it, while on ARM it has a fence
> both before and after it (per...
2014 Aug 08
2
[LLVMdev] Plan to optimize atomics in LLVM
> Longer term, I hope to improve the fence elimination of the ARM backend with
> a kind of PRE algorithm. Both of these improvements to the ARM backend
> should be fairly straightforward to port to the POWER architecture later,
> and I hope to also do that.
>
> Any reason these couldn't be done at the IR level?
I definitely agree here. At the time, it was a plausible idea