search for: x86emul_okay

...r, vmovdqu_to_mem, 15); + memset(res, 0x55, 128); + memset(res + 16, 0xff, 16); + memset(res + 20, 0x00, 16); + regs.eip = (unsigned long)&instr[0]; + regs.ecx = (unsigned long)res; + rc = x86_emulate(&ctxt, &emulops); + if ( (rc != X86EMUL_OKAY) || memcmp(res, res + 16, 64) ) + goto fail; + printf("okay\n"); + } + else + printf("skipped\n"); + + printf("%-40s", "Testing vmovdqu (%edx),%ymm4..."); + if ( stack_exec && cpu_has_avx ) + { + extern c...

...is atomic. Signed-off-by: Patrick Colp <Patrick.Colp@citrix.com> diff -r 68e8b8379244 -r 684c8fc69d65 xen/arch/x86/hvm/emulate.c --- a/xen/arch/x86/hvm/emulate.c Sun Aug 02 13:43:15 2009 +0100 +++ b/xen/arch/x86/hvm/emulate.c Thu Aug 06 11:39:37 2009 +0100 @@ -520,6 +520,183 @@ return X86EMUL_OKAY; } +/* Translate a VA to an MFN, injecting a page-fault if we fail */ +#define BAD_GVA_TO_GFN (~0UL) +#define BAD_GFN_TO_MFN (~1UL) +#define READONLY_GFN (~2UL) +static mfn_t emulate_gva_to_mfn( + struct vcpu *v, + unsigned long vaddr) +{ + unsigned long gfn; + mfn_t mfn; + p2m_...

..._restore(flags); } + +int msix_post_handler(struct vcpu *v) +{ + int rc; + + if ( v->arch.pending_msix_unmask.valid == 0 ) + return 0; + + v->arch.pending_msix_unmask.valid = 0; + + rc = msixtbl_write(v, v->arch.pending_msix_unmask.ctrl_address, 4, 0); + return rc != X86EMUL_OKAY ? -1 : 0; +} + diff --git a/xen/include/asm-x86/domain.h b/xen/include/asm-x86/domain.h index 9d39061..89b1adc 100644 --- a/xen/include/asm-x86/domain.h +++ b/xen/include/asm-x86/domain.h @@ -375,6 +375,12 @@ struct pv_vcpu spinlock_t shadow_ldt_lock; }; +struct pending_msix_unmask_info +{ +...

...e the matching irq_desc). */ spin_lock_irqsave(&desc->lock, flags); orig = readl(virt); val &= ~PCI_MSIX_VECTOR_BITMASK; val |= orig & PCI_MSIX_VECTOR_BITMASK; writel(val, virt); spin_unlock_irqrestore(&desc->lock, flags); #endif r = X86EMUL_OKAY; Thanks. Chien

...ore(flags); } + +bool_t msix_post_handler(struct vcpu *v) +{ + unsigned long ctrl_address = v->arch.pending_msix_unmask.ctrl_address; + + if ( ctrl_address == 0 ) + return 1; + + v->arch.pending_msix_unmask.ctrl_address = 0; + return msixtbl_write(v, ctrl_address, 4, 0) == X86EMUL_OKAY; +} + diff --git a/xen/include/asm-x86/domain.h b/xen/include/asm-x86/domain.h index 9d39061..8292fdb 100644 --- a/xen/include/asm-x86/domain.h +++ b/xen/include/asm-x86/domain.h @@ -375,6 +375,11 @@ struct pv_vcpu spinlock_t shadow_ldt_lock; }; +struct pending_msix_unmask_info +{ + unsig...

The first and third patches are cleaned up versions of an earlier v3 submission by Yang. 1: Nested VMX: check VMX capability before read VMX related MSRs 2: VMX: clean up capability checks 3: Nested VMX: fix IA32_VMX_CR4_FIXED1 msr emulation 4: x86: make hvm_cpuid() tolerate NULL pointers Signed-off-by: Jan Beulich <jbeulich@suse.com>

...t; :: "m" (res[10]), "c" (NULL) ); + + memcpy(instr, movsd_to_mem, 15); + regs.eip = (unsigned long)&instr[0]; + regs.ecx = (unsigned long)(res + 2); + regs.edx = 0; + rc = x86_emulate(&ctxt, &emulops); + if ( (rc != X86EMUL_OKAY) || memcmp(res, res + 8, 32) ) + goto fail; + printf("okay\n"); + } + else + { + printf("skipped\n"); + memset(res + 2, 0x66, 8); + } + + printf("%-40s", "Testing movaps (%edx),%xmm7..."); + if ( stack_exec &a...

...curr->domain->arch.hvm_domain; + struct domain *cd = current->domain; char c = *val; BUG_ON(bytes != 1); @@ -495,17 +494,16 @@ static int hvm_print_line( if ( !isprint(c) && (c != ''\n'') && (c != ''\t'') ) return X86EMUL_OKAY; - spin_lock(&hd->pbuf_lock); - hd->pbuf[hd->pbuf_idx++] = c; - if ( (hd->pbuf_idx == (HVM_PBUF_SIZE - 2)) || (c == ''\n'') ) + spin_lock(&cd->pbuf_lock); + if ( c != ''\n'' ) + cd->pbuf[cd->pbuf_idx++] = c; + i...

Changes from v2 to v3: - Use pfn_to_paddr() to get the address from frame number instead of doing shift directly. - Remove some unnecessary initialization code and add "static" to vmentry_fields and gpdptr_fields. - Enable the VMREAD/VMWRITE bitmap only if nested hvm is enabled. - Use clear_page() to set all 0 to the page instead of memset(). - Use domheap to allocate the

...curr->domain->arch.hvm_domain; + struct domain *cd = current->domain; char c = *val; BUG_ON(bytes != 1); @@ -495,17 +494,16 @@ static int hvm_print_line( if ( !isprint(c) && (c != ''\n'') && (c != ''\t'') ) return X86EMUL_OKAY; - spin_lock(&hd->pbuf_lock); - hd->pbuf[hd->pbuf_idx++] = c; - if ( (hd->pbuf_idx == (HVM_PBUF_SIZE - 2)) || (c == ''\n'') ) + spin_lock(&cd->pbuf_lock); + if ( c != ''\n'' ) + cd->pbuf[cd->pbuf_idx++] = c; + i...

This series of patches fix the mistake for debug exception(#DB), overflow exception(#OF) and INT3(#BP), INTn instruction emulation. Introduce new function vmx_inject_sw_exception() which deliver the software excetion, software interrupt and privileged software exception. Split hardware exception as a seperate function(old function vmx_inject_hw_exception()). Also Passed down intruction length

Changes from v1: - Define new struct hvm_trap to represent information of trap, include instruction length. - Renames hvm_inject_exception to hvm_inject_trap. Then define a couple of wrappers around that function for existing callers, so that their parameter lists actually *shrink*. This series of patches fix the mistake for debug exception(#DB), overflow exception(#OF) and INT3(#BP),

..., pl1e, ol1e, nl1e, page_to_mfn(page), v) ) + if ( !UPDATE_ENTRY(l1, pl1e, ol1e, nl1e, mfn, v) ) BUG(); } unmap_domain_page(pl1e); /* Finally, drop the old PTE. */ - put_page_from_l1e(gl1e_to_ml1e(d, ol1e), d); + put_page_from_l1e(ol1e, d); return X86EMUL_OKAY; } @@ -3365,17 +3366,13 @@ int ptwr_do_page_fault(struct vcpu *v, u LOCK_BIGLOCK(d); - /* - * Attempt to read the PTE that maps the VA being accessed. By checking for - * PDE validity in the L2 we avoid many expensive fixups in __get_user(). - */ + /* Attempt to read the...

...st be handled in the emulation code in order to avoid running into problems on newer CPUs. Signed-off-by: Jan Beulich <jbeulich@suse.com> --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -1058,6 +1058,9 @@ static bool_t vcpu_has( return rc == X86EMUL_OKAY; } +#define vcpu_has_lzcnt() vcpu_has(0x80000001, ECX, 5, ctxt, ops) +#define vcpu_has_bmi1() vcpu_has(0x00000007, EBX, 3, ctxt, ops) + #define vcpu_must_have(leaf, reg, bit) \ generate_exception_if(!vcpu_has(leaf, reg, bit, ctxt, ops), EXC_UD, -1) #define vcpu_must_have_mmx() vcpu_mu...

...0, modrm_mod = 0, modrm_reg = 0, modrm_rm = 0; union vex vex = {}; unsigned int op_bytes, def_op_bytes, ad_bytes, def_ad_bytes; -#define REPE_PREFIX 1 -#define REPNE_PREFIX 2 - unsigned int lock_prefix = 0, rep_prefix = 0; + bool_t lock_prefix = 0; int override_seg = -1, rc = X86EMUL_OKAY; struct operand src, dst; DECLARE_ALIGNED(mmval_t, mmval); @@ -1359,7 +1361,8 @@ x86_emulate( { case 0x66: /* operand-size override */ op_bytes = def_op_bytes ^ 6; - vex.pfx = vex_66; + if ( !vex.pfx ) + vex.pfx = vex_66;...

Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> -- ---to satisfy European Law for business letters: Advanced Micro Devices GmbH Einsteinring 24, 85609 Dornach b. Muenchen Geschaeftsfuehrer: Alberto Bozzo, Andrew Bowd Sitz: Dornach, Gemeinde Aschheim, Landkreis Muenchen Registergericht Muenchen, HRB Nr. 43632 _______________________________________________ Xen-devel mailing list

From: Zhang Xiantao <xiantao.zhang@intel.com> With virtual EPT support, L1 hyerpvisor can use EPT hardware for L2 guest''s memory virtualization. In this way, L2 guest''s performance can be improved sharply. According to our testing, some benchmarks can show > 5x performance gain. Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com> Zhang Xiantao (11):

I ran a bisect to find out when Windows XP 32 bit becomes unusably slow. And I found the changeset that caused it. ========== The problem: ========== Windows 8 64 bit and 32 bit run fast and fine in the newest xen versions. Windows XP 32 bit runs unusably slow in anything new that I built from xen-unstable, but runs fast in 4.1.2 and 4.1.3 stable. While it is running slow, "xm top" or

...,10 @@ int hvm_set_cr3(unsigned long value) HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx", value); } + old=v->arch.hvm_vcpu.guest_cr[3]; v->arch.hvm_vcpu.guest_cr[3] = value; paging_update_cr3(v); + hvm_memory_event_cr3(value, old); return X86EMUL_OKAY; bad_cr3: @@ -1818,6 +1821,7 @@ int hvm_set_cr4(unsigned long value) v->arch.hvm_vcpu.guest_cr[4] = value; hvm_update_guest_cr(v, 4); + hvm_memory_event_cr4(value, old_cr); /* * Modifying CR4.{PSE,PAE,PGE,SMEP}, or clearing CR4.PCIDE

...emulator.c =================================================================== --- 2008-04-15.orig/tools/tests/test_x86_emulator.c 2008-04-01 11:10:21.000000000 +0200 +++ 2008-04-15/tools/tests/test_x86_emulator.c 2008-04-15 08:48:15.000000000 +0200 @@ -74,7 +74,7 @@ static int cmpxchg( return X86EMUL_OKAY; } -static int cmpxchg8b( +static int cmpxchg2( unsigned int seg, unsigned long offset, unsigned long old_lo, @@ -94,7 +94,7 @@ static struct x86_emulate_ops emulops = .insn_fetch = read, .write = write, .cmpxchg = cmpxchg, - .cmpxchg8b = cmpxchg8b +...