Displaying 18 results from an estimated 18 matches for "x86attinstprint".
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x86attinstprinter
2018 Jun 30
2
Using BuildMI to insert Intel MPX instruction BNDCU failed
...teCommon<llvm::MCOperand,
void>::operator[](unsigned long) const
/home/shenyouren/workspace/llvm/include/llvm/ADT/SmallVector.h:154:0
#10 0x00000000016b63bb llvm::MCInst::getOperand(unsigned int) const
/home/shenyouren/workspace/llvm/include/llvm/MC/MCInst.h:182:0
#11 0x00000000026695fd llvm::X86ATTInstPrinter::printOperand(llvm::MCInst
const*, unsigned int, llvm::raw_ostream&)
/home/shenyouren/workspace/llvm/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp:185:0
#12 0x0000000002664c06
llvm::X86ATTInstPrinter::printInstruction(llvm::MCInst const*,
llvm::raw_ostream&)
/home/shenyouren/workspace/...
2010 Jul 07
0
[LLVMdev] LLC Bug x86 with thread local storage
...%ecx
> 9: movq %fs:0, %rax
Which one is correct ?
- movl $tm_nest_level at TPOFF, %ecx
or
- movq $tm_nest_level at TPOFF, %rcx
or
- movl tm_nest_level at TPOFF, %ecx
Otherwise, Is there a way to remove this $ character?
I found that it is here in lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp
void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) {
O << '%' << getRegisterName(Op.getReg());
} else if (Op.isI...
2018 Feb 07
2
retpoline mitigation and 6.0
...se 'q':
// Print 64-bit register names if 64-bit integer registers are available.
// Otherwise, print 32-bit register names.
@@ -391,7 +396,10 @@ static bool printAsmMRegister(X86AsmPrinter &P, const MachineOperand &MO,
break;
}
- O << '%' << X86ATTInstPrinter::getRegisterName(Reg);
+ if (emit_pct)
+ O << '%';
+
+ O << X86ATTInstPrinter::getRegisterName(Reg);
return false;
}
@@ -464,6 +472,7 @@ bool X86AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
case 'w': // Print HImode register
c...
2010 Jun 22
2
[LLVMdev] LLC Bug x86 with thread local storage
On 06/21/2010 08:21 PM, Eric Christopher wrote:
> On Jun 21, 2010, at 2:56 AM, Patrick Marlier wrote:
>
>
>> Hello,
>>
>> This bug affects all LLVM versions from 2.6 to trunk :
>> http://llvm.org/bugs/show_bug.cgi?id=5081
>>
>> The workaround I found is to add this :
>>
>> Index: lib/Target/X86/X86Instr64bit.td
>>
2010 Jul 07
4
[LLVMdev] LLC Bug x86 with thread local storage
...ovl tm_nest_level at TPOFF, %ecx
>
I believe this is initial exec and so from:
http://people.redhat.com/drepper/tls.pdf
it would be movl tm_nest_level at TPOFF, %ecx
> Otherwise, Is there a way to remove this $ character?
>
> I found that it is here in lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp
>
> void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
> raw_ostream &O) {
> const MCOperand &Op = MI->getOperand(OpNo);
> if (Op.isReg()) {
> O << '%' << getRegisterName(Op.getReg())...
2010 Jul 07
0
[LLVMdev] LLC Bug x86 with thread local storage
...>
> I believe this is initial exec and so from:
>
> http://people.redhat.com/drepper/tls.pdf
>
> it would be movl tm_nest_level at TPOFF, %ecx
>
>> Otherwise, Is there a way to remove this $ character?
>>
>> I found that it is here in lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp
>>
>> void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
>> raw_ostream&O) {
>> const MCOperand&Op = MI->getOperand(OpNo);
>> if (Op.isReg()) {
>> O<< '%'<< get...
2018 Feb 07
0
retpoline mitigation and 6.0
...egister names if 64-bit integer registers are
> available.
> // Otherwise, print 32-bit register names.
> @@ -391,7 +396,10 @@ static bool printAsmMRegister(X86AsmPrinter &P, const
> MachineOperand &MO,
> break;
> }
>
> - O << '%' << X86ATTInstPrinter::getRegisterName(Reg);
> + if (emit_pct)
> + O << '%';
> +
> + O << X86ATTInstPrinter::getRegisterName(Reg);
> return false;
> }
>
> @@ -464,6 +472,7 @@ bool X86AsmPrinter::PrintAsmOperand(const MachineInstr
> *MI, unsigned OpNo,
> c...
2018 Feb 07
0
retpoline mitigation and 6.0
...ase 'q':
// Print 64-bit register names if 64-bit integer registers are
available.
// Otherwise, print 32-bit register names.
@@ -391,7 +396,10 @@ static bool printAsmMRegister(X86AsmPrinter &P, const
MachineOperand &MO,
break;
}
- O << '%' << X86ATTInstPrinter::getRegisterName(Reg);
+ if (EmitPercent)
+ O << '%';
+
+ O << X86ATTInstPrinter::getRegisterName(Reg);
return false;
}
~Craig
On Wed, Feb 7, 2018 at 3:40 PM, David Woodhouse via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> On Wed, 2018-02-07 at 23:30...
2018 Feb 07
2
retpoline mitigation and 6.0
On Wed, 2018-02-07 at 23:30 +0000, Chandler Carruth wrote:
> This should go to llvm-commits as a proper review. Do you want to do
> that David? Want someone on our end to pick it up?
I'll attempt to add some test cases...
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2013 Oct 28
2
[LLVMdev] Are Opcode and register mappings exposed anywhere?
...lvm-mirror/blob/master/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp. It looks like getRegisterName might do what you want, but I don't know where it's coming from. (Whether it's a function or a member of a super class. Hopefully, if it's a member, it's public.)
Looks like X86ATTInstPrinter::getRegisterName() and X86IntelInstPrinter::getRegisterName() are static, public members. It would still be handy to expose an enum somewhere. This is to support something like:
if (Inst.getOpcode() == X86::CALL64r) {
if (Inst.getOperand(0).getReg() == X86::RIP) {
// ...
}
}
E.g., expos...
2018 Feb 07
0
retpoline mitigation and 6.0
On Wed, 2018-02-07 at 13:16 -0800, Guenter Roeck wrote:
> Here are my exact versions:
> llvm: 3afd566557f3 ("AMDGPU: Add 32-bit constant address space")
> clang: 848874aed95a ("[clang-format] Fix ObjC message arguments formatting.")
OK, mine are slightly newer than that now, but I now get a working 64-
bit defconfig build. It'll still break with any PV
2018 Feb 07
3
retpoline mitigation and 6.0
On Wed, Feb 07, 2018 at 08:44:32PM +0000, David Woodhouse wrote:
> On Wed, 2018-02-07 at 10:11 -0800, Guenter Roeck wrote:
>
> > On Wed, Feb 07, 2018 at 10:49:25AM +0000, David Woodhouse wrote:
> > > Hm, please could we also have the %V asm constraint modifier? That
> > > allows us to emit calls to the thunks from inline asm using the
> > > register that the
2014 Jun 26
2
[LLVMdev] problem with X86's AVX assembler?
On Thu, Jun 26, 2014 at 10:23 AM, Adam Nemet <anemet at apple.com> wrote:
>
>
> On Jun 25, 2014, at 7:05 PM, Jun Koi <junkoi2004 at gmail.com> wrote:
>
>
>
>
> On Thu, Jun 26, 2014 at 5:47 AM, Adam Nemet <anemet at apple.com> wrote:
>
>> Hi Jun,
>>
>> On Jun 25, 2014, at 8:14 AM, Jun Koi <junkoi2004 at gmail.com> wrote:
>>
2013 Oct 29
0
[LLVMdev] Are Opcode and register mappings exposed anywhere?
...ib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp.
> It looks like getRegisterName might do what you want, but I don't know
> where it's coming from. (Whether it's a function or a member of a super
> class. Hopefully, if it's a member, it's public.)
>
> Looks like X86ATTInstPrinter::getRegisterName() and
> X86IntelInstPrinter::getRegisterName() are static, public members. It would
> still be handy to expose an enum somewhere. This is to support something
> like:
>
> if (Inst.getOpcode() == X86::CALL64r) {
> if (Inst.getOperand(0).getReg() == X86::RIP) {...
2013 Oct 28
0
[LLVMdev] Are Opcode and register mappings exposed anywhere?
See the source here:
https://github.com/earl/llvm-mirror/blob/master/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp.
It looks like getRegisterName might do what you want, but I don't know
where it's coming from. (Whether it's a function or a member of a super
class. Hopefully, if it's a member, it's public.)
PS Sorry for the duplicate, Stephen. I forgot to CC the list.
On
2013 Oct 28
2
[LLVMdev] Are Opcode and register mappings exposed anywhere?
I'm iterating over MCInsts and I'd like to examine particular instructions. For example, I'd like to look at all x86 CALL64m instructions. I may be missing something, but it seems like my only option is to use MCInstPrinter::getOpcodeName and compare strings. (Of course, I could iterate through the opcodes and build up a table of the ones I'm interested in to avoid string
2014 Apr 03
5
[LLVMdev] comparing .o files from different build trees
..../recurse2be/build/./lib/Target/X86/Release+Asserts/X86ISelDAGToDAG.o differ: byte 271126, line 2999
./lib/Target/X86/Release+Asserts/X86RegisterInfo.o ../../recurse2be/build/./lib/Target/X86/Release+Asserts/X86RegisterInfo.o differ: byte 33493, line 108
./lib/Target/X86/InstPrinter/Release+Asserts/X86ATTInstPrinter.o ../../recurse2be/build/./lib/Target/X86/InstPrinter/Release+Asserts/X86ATTInstPrinter.o differ: byte 93564, line 89
./lib/Target/X86/InstPrinter/Release+Asserts/X86IntelInstPrinter.o ../../recurse2be/build/./lib/Target/X86/InstPrinter/Release+Asserts/X86IntelInstPrinter.o differ: byte 107220, l...
2015 Jul 29
1
[LLVMdev] Error when i am using command make -j4 command in cygwin to compile safecode
...piling DwarfStringPool.cpp for Release+Asserts build
llvm[3]: Compiling LowerAtomic.cpp for Release+Asserts build
llvm[3]: Building Release+Asserts Archive Library libLLVMX86CodeGen.a
make[4]: Entering directory '/home/NIKHILREDDY/WORK/LLVM_OBJ/lib/Target/X86/InstPrinter'
llvm[4]: Compiling X86ATTInstPrinter.cpp for Release+Asserts build
llvm[3]: Compiling DwarfUnit.cpp for Release+Asserts build
llvm[3]: Compiling InstCombineMulDivRem.cpp for Release+Asserts build
llvm[3]: Compiling LowerExpectIntrinsic.cpp for Release+Asserts build
llvm[4]: Compiling X86InstComments.cpp for Release+Asserts build
llv...