search for: x86_trap_pf

Displaying 20 results from an estimated 32 matches for "x86_trap_pf".

2020 Apr 28
0
[PATCH v3 49/75] x86/sev-es: Handle instruction fetches from user-space
...a28c2 100644 --- a/arch/x86/kernel/sev-es.c +++ b/arch/x86/kernel/sev-es.c @@ -165,17 +165,30 @@ static enum es_result vc_decode_insn(struct es_em_ctxt *ctxt) enum es_result ret; int res; - res = vc_fetch_insn_kernel(ctxt, buffer); - if (unlikely(res == -EFAULT)) { - ctxt->fi.vector = X86_TRAP_PF; - ctxt->fi.error_code = 0; - ctxt->fi.cr2 = ctxt->regs->ip; - return ES_EXCEPTION; + if (!user_mode(ctxt->regs)) { + res = vc_fetch_insn_kernel(ctxt, buffer); + if (unlikely(res == -EFAULT)) { + ctxt->fi.vector = X86_TRAP_PF; + ctxt->fi.error_code = 0; +...
2020 Apr 28
0
[PATCH v3 40/75] x86/sev-es: Compile early handler code into kernel image
...signed char *)ctxt->regs->ip, + MAX_INSN_SIZE); +} + +static enum es_result vc_decode_insn(struct es_em_ctxt *ctxt) +{ + char buffer[MAX_INSN_SIZE]; + enum es_result ret; + int res; + + res = vc_fetch_insn_kernel(ctxt, buffer); + if (unlikely(res == -EFAULT)) { + ctxt->fi.vector = X86_TRAP_PF; + ctxt->fi.error_code = 0; + ctxt->fi.cr2 = ctxt->regs->ip; + return ES_EXCEPTION; + } + + insn_init(&ctxt->insn, buffer, MAX_INSN_SIZE - res, 1); + insn_get_length(&ctxt->insn); + + ret = ctxt->insn.immediate.got ? ES_OK : ES_DECODE_FAILED; + + return ret; +...
2020 Feb 11
0
[PATCH 38/62] x86/sev-es: Handle instruction fetches from user-space
...= rip[offset]; + if (user_mode(ctxt->regs)) { + unsigned long addr = ctxt->regs->ip + offset; + char __user *rip = (char __user *)addr; + + if (unlikely(addr >= TASK_SIZE_MAX)) + return ES_UNSUPPORTED; + + if (copy_from_user(buffer + offset, rip, 1)) { + ctxt->fi.vector = X86_TRAP_PF; + ctxt->fi.cr2 = addr; + ctxt->fi.error_code = X86_PF_INSTR | X86_PF_USER; + return ES_EXCEPTION; + } + } else { + char *rip = (char *)ctxt->regs->ip + offset; + + if (probe_kernel_read(buffer + offset, rip, 1) != 0) { + ctxt->fi.vector = X86_TRAP_PF; + ctxt-...
2017 Nov 17
2
[PATCH RFC v3 3/6] sched/idle: Add a generic poll before enter real idle path
...Xen guys, who has implemented the paravirt framework. I can implement it as easy as following: ???????????? --- a/arch/x86/kernel/kvm.c ???????????? +++ b/arch/x86/kernel/kvm.c ???????????? @@ -465,6 +465,12 @@ static void __init kvm_apf_trap_init(void) ???????????????????? update_intr_gate(X86_TRAP_PF, async_page_fault); ????????????? } ???????????? +static __cpuidle void kvm_safe_halt(void) ???????????? +{ ??? ???? +??????? /* 1. POLL, if need_resched() --> return */ ??? ???? + ???????????? +??????? asm volatile("sti; hlt": : :"memory"); /* 2. halt */ ????????????...
2017 Nov 17
2
[PATCH RFC v3 3/6] sched/idle: Add a generic poll before enter real idle path
...Xen guys, who has implemented the paravirt framework. I can implement it as easy as following: ???????????? --- a/arch/x86/kernel/kvm.c ???????????? +++ b/arch/x86/kernel/kvm.c ???????????? @@ -465,6 +465,12 @@ static void __init kvm_apf_trap_init(void) ???????????????????? update_intr_gate(X86_TRAP_PF, async_page_fault); ????????????? } ???????????? +static __cpuidle void kvm_safe_halt(void) ???????????? +{ ??? ???? +??????? /* 1. POLL, if need_resched() --> return */ ??? ???? + ???????????? +??????? asm volatile("sti; hlt": : :"memory"); /* 2. halt */ ????????????...
2020 Feb 11
0
[PATCH 30/62] x86/head/64: Move early exception dispatch to C code
....h> /* * Manage page tables very early on. @@ -377,6 +379,24 @@ int __init early_make_pgtable(unsigned long address) return __early_make_pgtable(address, pmd); } +void __init early_exception(struct pt_regs *regs, int trapnr) +{ + unsigned long cr2; + int r; + + switch (trapnr) { + case X86_TRAP_PF: + cr2 = native_read_cr2(); + r = early_make_pgtable(cr2); + break; + default: + r = 1; + } + + if (r) + early_fixup_exception(regs, trapnr); +} + /* Don't add a printk in there. printk relies on the PDA which is not initialized yet. */ static void __init clear_bss(void) diff --git...
2020 Feb 11
1
[PATCH 30/62] x86/head/64: Move early exception dispatch to C code
On Tue, Feb 11, 2020 at 5:53 AM Joerg Roedel <joro at 8bytes.org> wrote: > > From: Joerg Roedel <jroedel at suse.de> > > Move the assembly coded dispatch between page-faults and all other > exceptions to C code to make it easier to maintain and extend. > > Signed-off-by: Joerg Roedel <jroedel at suse.de> > --- > arch/x86/kernel/head64.c | 20
2020 Jul 22
0
[PATCH v4 51/75] x86/sev-es: Handle MMIO events
...l vc_slow_virt_to_phys(struct ghcb *ghcb, struct es_em_ctxt *ctxt, pgd_t *pgd; pte_t *pte; - pgd = pgd_offset(current->active_mm, va); + pgd = __va(read_cr3_pa()); + pgd = &pgd[pgd_index(va)]; pte = lookup_address_in_pgd(pgd, va, &level); if (!pte) { ctxt->fi.vector = X86_TRAP_PF;
2020 May 20
1
[PATCH v3 51/75] x86/sev-es: Handle MMIO events
On Tue, Apr 28, 2020 at 05:17:01PM +0200, Joerg Roedel wrote: > From: Tom Lendacky <thomas.lendacky at amd.com> > > Add handler for VC exceptions caused by MMIO intercepts. These > intercepts come along as nested page faults on pages with reserved > bits set. > > Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com> > [ jroedel at suse.de: Adapt to VC
2020 Jul 14
0
[PATCH v4 14/75] x86/boot/compressed/64: Add page-fault handler
...6/boot/compressed/idt_64.c b/arch/x86/boot/compressed/idt_64.c index 082cd6bca033..5f083092a86d 100644 --- a/arch/x86/boot/compressed/idt_64.c +++ b/arch/x86/boot/compressed/idt_64.c @@ -40,5 +40,7 @@ void load_stage2_idt(void) { boot_idt_desc.address = (unsigned long)boot_idt; + set_idt_entry(X86_TRAP_PF, boot_page_fault); + load_boot_idt(&boot_idt_desc); } diff --git a/arch/x86/boot/compressed/idt_handlers_64.S b/arch/x86/boot/compressed/idt_handlers_64.S index 36dee2f40a8b..b20e57504a94 100644 --- a/arch/x86/boot/compressed/idt_handlers_64.S +++ b/arch/x86/boot/compressed/idt_handlers_64.S...
2017 Nov 17
0
[PATCH RFC v3 3/6] sched/idle: Add a generic poll before enter real idle path
...easy as following: > > ???????????? --- a/arch/x86/kernel/kvm.c Your email client is using a very strange formatting. > ???????????? +++ b/arch/x86/kernel/kvm.c > ???????????? @@ -465,6 +465,12 @@ static void __init kvm_apf_trap_init(void) > ???????????????????? update_intr_gate(X86_TRAP_PF, async_page_fault); > ????????????? } > > ???????????? +static __cpuidle void kvm_safe_halt(void) > ???????????? +{ > ??? ???? +??????? /* 1. POLL, if need_resched() --> return */ > ??? ???? + > ???????????? +??????? asm volatile("sti; hlt": : :"memory")...
2020 Apr 02
0
[PATCH 14/70] x86/boot/compressed/64: Add page-fault handler
...ot/compressed/idt_64.c > index 46ecea671b90..84ba57d9d436 100644 > --- a/arch/x86/boot/compressed/idt_64.c > +++ b/arch/x86/boot/compressed/idt_64.c > @@ -39,5 +39,7 @@ void load_stage2_idt(void) > { > boot_idt_desc.address = (unsigned long)boot_idt; > > + set_idt_entry(X86_TRAP_PF, boot_pf_handler); > + > load_boot_idt(&boot_idt_desc); > } > diff --git a/arch/x86/boot/compressed/idt_handlers_64.S b/arch/x86/boot/compressed/idt_handlers_64.S > index 3d86ab35ef52..bfb3fc5aa144 100644 > --- a/arch/x86/boot/compressed/idt_handlers_64.S > +++ b/arch/x8...
2020 May 20
2
[PATCH v3 42/75] x86/sev-es: Setup GHCB based boot #VC handler
...-ghcb public */ > + boot_ghcb = &boot_ghcb_page; > + > + return true; > +} > + > +static void __init vc_early_vc_forward_exception(struct es_em_ctxt *ctxt) That second "vc" looks redundant. > +{ > + int trapnr = ctxt->fi.vector; > + > + if (trapnr == X86_TRAP_PF) > + native_write_cr2(ctxt->fi.cr2); > + > + ctxt->regs->orig_ax = ctxt->fi.error_code; > + do_early_exception(ctxt->regs, trapnr); > +} > + > +static enum es_result vc_handle_exitcode(struct es_em_ctxt *ctxt, > + struct ghcb *ghcb, > + unsigned...
2020 May 20
2
[PATCH v3 42/75] x86/sev-es: Setup GHCB based boot #VC handler
...-ghcb public */ > + boot_ghcb = &boot_ghcb_page; > + > + return true; > +} > + > +static void __init vc_early_vc_forward_exception(struct es_em_ctxt *ctxt) That second "vc" looks redundant. > +{ > + int trapnr = ctxt->fi.vector; > + > + if (trapnr == X86_TRAP_PF) > + native_write_cr2(ctxt->fi.cr2); > + > + ctxt->regs->orig_ax = ctxt->fi.error_code; > + do_early_exception(ctxt->regs, trapnr); > +} > + > +static enum es_result vc_handle_exitcode(struct es_em_ctxt *ctxt, > + struct ghcb *ghcb, > + unsigned...
2020 Aug 24
0
[PATCH v6 52/76] x86/sev-es: Handle MMIO events
...vaddr, phys_addr_t *paddr) +{ + unsigned long va = (unsigned long)vaddr; + unsigned int level; + phys_addr_t pa; + pgd_t *pgd; + pte_t *pte; + + pgd = __va(read_cr3_pa()); + pgd = &pgd[pgd_index(va)]; + pte = lookup_address_in_pgd(pgd, va, &level); + if (!pte) { + ctxt->fi.vector = X86_TRAP_PF; + ctxt->fi.cr2 = vaddr; + ctxt->fi.error_code = 0; + + if (user_mode(ctxt->regs)) + ctxt->fi.error_code |= X86_PF_USER; + + return false; + } + + pa = (phys_addr_t)pte_pfn(*pte) << PAGE_SHIFT; + pa |= va & ~page_level_mask(level); + + *paddr = pa; + + return true...
2017 Nov 16
1
[PATCH RFC v3 3/6] sched/idle: Add a generic poll before enter real idle path
On 2017-11-16 06:03, Thomas Gleixner wrote: > On Wed, 15 Nov 2017, Peter Zijlstra wrote: > >> On Mon, Nov 13, 2017 at 06:06:02PM +0800, Quan Xu wrote: >>> From: Yang Zhang <yang.zhang.wz at gmail.com> >>> >>> Implement a generic idle poll which resembles the functionality >>> found in arch/. Provide weak arch_cpu_idle_poll function which
2020 Apr 28
0
[PATCH v3 42/75] x86/sev-es: Setup GHCB based boot #VC handler
...on is cleared. + */ + memset(&boot_ghcb_page, 0, PAGE_SIZE); + + /* Alright - Make the boot-ghcb public */ + boot_ghcb = &boot_ghcb_page; + + return true; +} + +static void __init vc_early_vc_forward_exception(struct es_em_ctxt *ctxt) +{ + int trapnr = ctxt->fi.vector; + + if (trapnr == X86_TRAP_PF) + native_write_cr2(ctxt->fi.cr2); + + ctxt->regs->orig_ax = ctxt->fi.error_code; + do_early_exception(ctxt->regs, trapnr); +} + +static enum es_result vc_handle_exitcode(struct es_em_ctxt *ctxt, + struct ghcb *ghcb, + unsigned long exit_code) +{ + enum es_result result; +...
2020 May 12
2
[PATCH v3 23/75] x86/boot/compressed/64: Setup GHCB Based VC Exception handler
...gt; diff --git a/arch/x86/boot/compressed/idt_64.c b/arch/x86/boot/compressed/idt_64.c > index f8295d68b3e1..44d20c4f47c9 100644 > --- a/arch/x86/boot/compressed/idt_64.c > +++ b/arch/x86/boot/compressed/idt_64.c > @@ -45,5 +45,9 @@ void load_stage2_idt(void) > > set_idt_entry(X86_TRAP_PF, boot_page_fault); > > +#ifdef CONFIG_AMD_MEM_ENCRYPT > + set_idt_entry(X86_TRAP_VC, boot_stage2_vc); > +#endif if IS_ENABLED()... ... > +static enum es_result vc_decode_insn(struct es_em_ctxt *ctxt) > +{ > + char buffer[MAX_INSN_SIZE]; > + enum es_result ret; > + &g...
2020 May 12
2
[PATCH v3 23/75] x86/boot/compressed/64: Setup GHCB Based VC Exception handler
...gt; diff --git a/arch/x86/boot/compressed/idt_64.c b/arch/x86/boot/compressed/idt_64.c > index f8295d68b3e1..44d20c4f47c9 100644 > --- a/arch/x86/boot/compressed/idt_64.c > +++ b/arch/x86/boot/compressed/idt_64.c > @@ -45,5 +45,9 @@ void load_stage2_idt(void) > > set_idt_entry(X86_TRAP_PF, boot_page_fault); > > +#ifdef CONFIG_AMD_MEM_ENCRYPT > + set_idt_entry(X86_TRAP_VC, boot_stage2_vc); > +#endif if IS_ENABLED()... ... > +static enum es_result vc_decode_insn(struct es_em_ctxt *ctxt) > +{ > + char buffer[MAX_INSN_SIZE]; > + enum es_result ret; > + &g...
2020 Sep 07
0
[PATCH v7 40/72] x86/sev-es: Setup GHCB based boot #VC handler
...ction is cleared. + */ + memset(&boot_ghcb_page, 0, PAGE_SIZE); + + /* Alright - Make the boot-ghcb public */ + boot_ghcb = &boot_ghcb_page; + + return true; +} + +static void __init vc_early_forward_exception(struct es_em_ctxt *ctxt) +{ + int trapnr = ctxt->fi.vector; + + if (trapnr == X86_TRAP_PF) + native_write_cr2(ctxt->fi.cr2); + + ctxt->regs->orig_ax = ctxt->fi.error_code; + do_early_exception(ctxt->regs, trapnr); +} + +static enum es_result vc_handle_exitcode(struct es_em_ctxt *ctxt, + struct ghcb *ghcb, + unsigned long exit_code) +{ + enum es_result result; +...