Displaying 7 results from an estimated 7 matches for "x86_subreg_8bit".
2008 Oct 15
2
[LLVMdev] INSERT_SUBREG node.
On Tue, 2008-10-14 at 10:19 -0700, Evan Cheng wrote:
> You need to specify sub-register == super-register, idx relationship.
> See X86RegisterInfo.td:
>
> def x86_subreg_8bit : PatLeaf<(i32 1)>;
> def x86_subreg_16bit : PatLeaf<(i32 2)>;
> def x86_subreg_32bit : PatLeaf<(i32 3)>;
>
> def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
> R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
>...
2008 Oct 15
0
[LLVMdev] INSERT_SUBREG node.
On Oct 15, 2008, at 5:29 AM, sanjiv gupta wrote:
> On Tue, 2008-10-14 at 10:19 -0700, Evan Cheng wrote:
>> You need to specify sub-register == super-register, idx relationship.
>> See X86RegisterInfo.td:
>>
>> def x86_subreg_8bit : PatLeaf<(i32 1)>;
>> def x86_subreg_16bit : PatLeaf<(i32 2)>;
>> def x86_subreg_32bit : PatLeaf<(i32 3)>;
>>
>> def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
>> R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
&g...
2008 Oct 14
0
[LLVMdev] INSERT_SUBREG node.
You need to specify sub-register == super-register, idx relationship.
See X86RegisterInfo.td:
def x86_subreg_8bit : PatLeaf<(i32 1)>;
def x86_subreg_16bit : PatLeaf<(i32 2)>;
def x86_subreg_32bit : PatLeaf<(i32 3)>;
def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
[AL, CL, DL, BL, SPL, BPL...
2008 Oct 13
2
[LLVMdev] INSERT_SUBREG node.
On Thu, 2008-10-02 at 11:19 -0700, Evan Cheng wrote:
>
> On Oct 2, 2008, at 11:02 AM, Sanjiv.Gupta at microchip.com wrote:
>
> > What’s the value produced by an INSERT_SUBREG node? Is it a chain?
>
>
> No, insert_subreg returns a value:
>
>
> v1 = insert_subreg v2, v3, idx
>
>
> v1 and v2 will have the same type, e.g. i16, and v3 must have a
>
2008 Oct 15
3
[LLVMdev] INSERT_SUBREG node.
...700, Evan Cheng wrote:
> On Oct 15, 2008, at 5:29 AM, sanjiv gupta wrote:
>
> > On Tue, 2008-10-14 at 10:19 -0700, Evan Cheng wrote:
> >> You need to specify sub-register == super-register, idx relationship.
> >> See X86RegisterInfo.td:
> >>
> >> def x86_subreg_8bit : PatLeaf<(i32 1)>;
> >> def x86_subreg_16bit : PatLeaf<(i32 2)>;
> >> def x86_subreg_32bit : PatLeaf<(i32 3)>;
> >>
> >> def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
> >> R8W, R9W, R10W, R11W, R1...
2009 Mar 17
0
[LLVMdev] Overlapping register classes
On Mar 16, 2009, at 11:31 AM, Jakob Stoklund Olesen wrote:
> Dan Gohman <gohman at apple.com> writes:
>
>> On Mar 15, 2009, at 2:02 PM, Jakob Stoklund Olesen wrote:
>>> Am I misusing register classes, or is this simply functionality that
>>> has not been written yet? The existing backends seem to have only
>>> one
>>> register class per
2009 Mar 16
2
[LLVMdev] Overlapping register classes
Dan Gohman <gohman at apple.com> writes:
> On Mar 15, 2009, at 2:02 PM, Jakob Stoklund Olesen wrote:
>> Am I misusing register classes, or is this simply functionality that
>> has not been written yet? The existing backends seem to have only one
>> register class per machine value type.
>
> The x86 backend has an example of a partial solution. The GR32
>