Displaying 8 results from an estimated 8 matches for "x86_subreg_32bit".
2008 Mar 19
2
[LLVMdev] SUBREG instructions and mayLoad/mayStore/etc.
...doesn't have the the
MayLoad flag set.
x86-64 does have a few variants of INSERT_SUBREG, and one of
them does have a load:
def : Pat<(i64 (anyext (loadi32 addr:$src))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV32rm addr:$src),
x86_subreg_32bit)>;
This isn't currently being reflected in the InstrInfo tables.
Naively, it seems like we should add a separate INSERT_SUBREGrm
instruction, and so on, or something like that, in order to be able
to have accurate InstrInfo tables. Does anyone familiar with the
new subregs infastructure hav...
2008 Oct 14
0
[LLVMdev] INSERT_SUBREG node.
You need to specify sub-register == super-register, idx relationship.
See X86RegisterInfo.td:
def x86_subreg_8bit : PatLeaf<(i32 1)>;
def x86_subreg_16bit : PatLeaf<(i32 2)>;
def x86_subreg_32bit : PatLeaf<(i32 3)>;
def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
[AL, CL, DL, BL, SPL, BPL, SIL, DIL,
R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
I admit the wa...
2008 Oct 15
2
[LLVMdev] INSERT_SUBREG node.
On Tue, 2008-10-14 at 10:19 -0700, Evan Cheng wrote:
> You need to specify sub-register == super-register, idx relationship.
> See X86RegisterInfo.td:
>
> def x86_subreg_8bit : PatLeaf<(i32 1)>;
> def x86_subreg_16bit : PatLeaf<(i32 2)>;
> def x86_subreg_32bit : PatLeaf<(i32 3)>;
>
> def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
> R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
> [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
> R8B, R9B, R10B, R11B, R12B, R13B, R14B, R...
2008 Oct 13
2
[LLVMdev] INSERT_SUBREG node.
On Thu, 2008-10-02 at 11:19 -0700, Evan Cheng wrote:
>
> On Oct 2, 2008, at 11:02 AM, Sanjiv.Gupta at microchip.com wrote:
>
> > What’s the value produced by an INSERT_SUBREG node? Is it a chain?
>
>
> No, insert_subreg returns a value:
>
>
> v1 = insert_subreg v2, v3, idx
>
>
> v1 and v2 will have the same type, e.g. i16, and v3 must have a
>
2008 Oct 15
0
[LLVMdev] INSERT_SUBREG node.
...Tue, 2008-10-14 at 10:19 -0700, Evan Cheng wrote:
>> You need to specify sub-register == super-register, idx relationship.
>> See X86RegisterInfo.td:
>>
>> def x86_subreg_8bit : PatLeaf<(i32 1)>;
>> def x86_subreg_16bit : PatLeaf<(i32 2)>;
>> def x86_subreg_32bit : PatLeaf<(i32 3)>;
>>
>> def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
>> R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
>> [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
>> R8B, R9B, R10B, R11B, R12...
2008 Mar 19
0
[LLVMdev] SUBREG instructions and mayLoad/mayStore/etc.
...>
>
> x86-64 does have a few variants of INSERT_SUBREG, and one of
> them does have a load:
>
> def : Pat<(i64 (anyext (loadi32 addr:$src))),
> (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV32rm addr:$src),
>
> x86_subreg_32bit)>;
>
>
> This isn't currently being reflected in the InstrInfo tables.
> Naively, it seems like we should add a separate INSERT_SUBREGrm
> instruction, and so on, or something like that, in order to be able
> to have accurate InstrInfo tables. Does anyone familiar with the...
2008 Apr 03
7
[LLVMdev] alias information in codegen
...formation about
memory accesses.
This is being addressed by MemOperands. However, currently there is a
problem; the current code misses memory references in anonymous
patterns, like this in x86:
def : Pat<(zextloadi64i32 addr:$src),
(SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
x86_subreg_32bit)>;
I can provide more details about what's going on here if anyone's
interested.
However, for people just interested in post-regalloc scheduling and
VLIW packing and similar things, MemOperands aren't the only approach.
A potentially better way to do this would be to extend Machine...
2008 Oct 15
3
[LLVMdev] INSERT_SUBREG node.
..., Evan Cheng wrote:
> >> You need to specify sub-register == super-register, idx relationship.
> >> See X86RegisterInfo.td:
> >>
> >> def x86_subreg_8bit : PatLeaf<(i32 1)>;
> >> def x86_subreg_16bit : PatLeaf<(i32 2)>;
> >> def x86_subreg_32bit : PatLeaf<(i32 3)>;
> >>
> >> def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
> >> R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
> >> [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
> >>...