search for: x86_segment

...86/mm.c 2008-04-11 14:48:16.000000000 +0200 +++ 2008-04-15/xen/arch/x86/mm.c 2008-04-15 08:48:15.000000000 +0200 @@ -3635,6 +3635,7 @@ static int ptwr_emulated_cmpxchg( container_of(ctxt, struct ptwr_emulate_ctxt, ctxt)); } +#ifdef __i386__ static int ptwr_emulated_cmpxchg8b( enum x86_segment seg, unsigned long offset, @@ -3650,13 +3651,16 @@ static int ptwr_emulated_cmpxchg8b( offset, ((u64)old_hi << 32) | old, ((u64)new_hi << 32) | new, 8, 1, container_of(ctxt, struct ptwr_emulate_ctxt, ctxt)); } +#else +#define ptwr_emulated_cmpxchg8b NULL +#endif...

....c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -709,8 +709,8 @@ static void vmx_ctxt_switch_to(struct vc .fields = { .type = 0xb, .s = 0, .dpl = 0, .p = 1, .avl = 0, \ .l = 0, .db = 0, .g = 0, .pad = 0 } }).bytes) -static void vmx_get_segment_register(struct vcpu *v, enum x86_segment seg, - struct segment_register *reg) +void vmx_get_segment_register(struct vcpu *v, enum x86_segment seg, + struct segment_register *reg) { uint32_t attr = 0; @@ -1461,11 +1461,6 @@ static int vmx_event_pending(struct vcpu...

...(u64) old_lo; + new = (((u64) new_hi) << 32) | (u64) new_lo; + + prev = cmpxchg(((u64 *)addr), old, new); + + if ( prev != old ) + rc = X86EMUL_CMPXCHG_FAILED; + + emulate_unmap_dest(v, addr, 8, sh_ctxt); + + return rc; +} +#endif + static int hvmemul_cmpxchg( enum x86_segment seg, unsigned long offset, @@ -528,8 +705,32 @@ unsigned int bytes, struct x86_emulate_ctxt *ctxt) { - /* Fix this in case the guest is really relying on r-m-w atomicity. */ - return hvmemul_write(seg, offset, p_new, bytes, ctxt); + struct hvm_emulate_ctxt *hvmemul_ctxt = +...

This patch series is a reworking of a series developed by Mukesh Rathor at Oracle. The entirety of the design and development was done by him; I have only reworked, reorganized, and simplified things in a way that I think makes more sense. The vast majority of the credit for this effort therefore goes to him. This version is labelled v13 because it is based on his most recent series, v11.

From: Yang Zhang <yang.z.zhang@Intel.com> The following patches fix the issue that fail to boot L2 guest on APIC-v available machine. The main problem is that with APIC-v, virtual interrupt inject L1 is totally through APIC-v. But if virtual interrupt is arrived when L2 is running, L1 will detect interrupt through vmexit with reason external interrupt. If this happens, we should update

From: Zhang Xiantao <xiantao.zhang@intel.com> With virtual EPT support, L1 hyerpvisor can use EPT hardware for L2 guest''s memory virtualization. In this way, L2 guest''s performance can be improved sharply. According to our testing, some benchmarks can show > 5x performance gain. Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com> Zhang Xiantao (11):

A character device for accessing (in user-space) pages that have been granted by other domains. Signed-off-by: Derek Murray <Derek.Murray@cl.cam.ac.uk> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel