Displaying 3 results from an estimated 3 matches for "x86_i32".
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x86_32
2009 Jun 13
0
[LLVMdev] Regular Expressions
...s! :)
However, I don't see any reason to base this off of strings. Instead
of passing down "f32" as a string, why not do something like this
pseudo code:
class X86ValueType {
RegisterClass RegClass;
...
}
def X86_f32 : X86ValueType {
let RegClass = FR32;
... };
def X86_i32 : X86ValueType { ... };
Then change fp_cvt_scalar_VXSnrr to be something like this:
> class fp_cvt_scalar_VXSnrr<
> // Parent: avx_fp_cvt_scalar_xs_node_rm_DEF_V#NAME#_128rr
> bits<8> opc,
> string OpcodeStr,
> SDNode OpNode,
> X86ValueType DstType,
> X86ValueTy...
2009 Jun 11
2
[LLVMdev] Regular Expressions
On Thursday 11 June 2009 12:28, Chris Lattner wrote:
> On Jun 9, 2009, at 12:39 PM, David Greene wrote:
> > On Tuesday 09 June 2009 14:34, Dan Gohman wrote:
> >> Can you describe what problem you're trying to solve here? Does it
> >> really need Regular Expressions?
> >
> > Yes. I want TableGen to be able to infer lots of stuff
> >
2009 Jun 15
2
[LLVMdev] Regular Expressions
...of strings. Instead
> of passing down "f32" as a string, why not do something like this
> pseudo code:
>
> class X86ValueType {
> RegisterClass RegClass;
> ...
> }
>
> def X86_f32 : X86ValueType {
> let RegClass = FR32;
> ... };
> def X86_i32 : X86ValueType { ... };
>
> Then change fp_cvt_scalar_VXSnrr to be something like this:
>
>> class fp_cvt_scalar_VXSnrr<
>> // Parent: avx_fp_cvt_scalar_xs_node_rm_DEF_V#NAME#_128rr
>> bits<8> opc,
>> string OpcodeStr,
>> SDNode OpNode,
>>...