Displaying 3 results from an estimated 3 matches for "x86_feature_sse4_1".
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x86_feature_sse4_2
2011 Nov 24
0
[PATCH 4/6] X86: Disable PCID/INVPCID for pv
...16 13 /* CMPXCHG16B */
#define X86_FEATURE_XTPR 14 /* Send Task Priority Messages */
#define X86_FEATURE_PDCM 15 /* Perf/Debug Capability MSR */
+#define X86_FEATURE_PCID 17 /* Process Context ID */
#define X86_FEATURE_DCA 18 /* Direct Cache Access */
#define X86_FEATURE_SSE4_1 19 /* Streaming SIMD Extensions 4.1 */
#define X86_FEATURE_SSE4_2 20 /* Streaming SIMD Extensions 4.2 */
@@ -132,5 +133,6 @@
#define X86_FEATURE_SMEP 7 /* Supervisor Mode Execution Protection */
#define X86_FEATURE_BMI2 8 /* 2nd group bit manipulation extensions */
#de...
2011 Nov 24
0
[PATCH 5/6] X86: Prepare PCID/INVPCID for hvm
...2011 +0800
@@ -311,6 +311,7 @@ static void xc_cpuid_hvm_policy(
bitmaskof(X86_FEATURE_SSSE3) |
bitmaskof(X86_FEATURE_FMA) |
bitmaskof(X86_FEATURE_CX16) |
+ bitmaskof(X86_FEATURE_PCID) |
bitmaskof(X86_FEATURE_SSE4_1) |
bitmaskof(X86_FEATURE_SSE4_2) |
bitmaskof(X86_FEATURE_MOVBE) |
@@ -363,6 +364,7 @@ static void xc_cpuid_hvm_policy(
bitmaskof(X86_FEATURE_SMEP) |
bitmaskof(X86_FEATURE_BMI2) |
bi...
2007 Aug 09
0
[PATCH] x86/hvm: miscellaneous CPUID handling changes
...ID (4*32+10) /* Context ID */
#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
+#define X86_FEATURE_PDCM (4*32+15) /* Perf/Debug Capability MSR */
+#define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */
+#define X86_FEATURE_SSE4_1 (4*32+19) /* Streaming SIMD Extensions 4.1 */
+#define X86_FEATURE_SSE4_2 (4*32+20) /* Streaming SIMD Extensions 4.2 */
+#define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */
/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
#define X86_FEATURE_XSTORE (5*32+ 2...