Displaying 3 results from an estimated 3 matches for "x86_feature_lahf_lm".
2010 Oct 07
0
[PATCH] x86-64: workaround for BIOSes wrongly enabling LAHF_LM feature indicator
...a two methods:
@@ -329,6 +370,24 @@ static void __devinit init_amd(struct cp
3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
clear_bit(0*32+31, c->x86_capability);
+#ifdef CONFIG_X86_64
+ if (c->x86 == 0xf && c->x86_model < 0x14
+ && cpu_has(c, X86_FEATURE_LAHF_LM)) {
+ /*
+ * Some BIOSes incorrectly force this feature, but only K8
+ * revision D (model = 0x14) and later actually support it.
+ * (AMD Erratum #110, docId: 25759).
+ */
+ unsigned int lo, hi;
+
+ clear_bit(X86_FEATURE_LAHF_LM, c->x86_capability);
+ if (!rdmsr_amd_safe(0xc001100d,...
2007 Aug 09
0
[PATCH] x86/hvm: miscellaneous CPUID handling changes
...( !v->domain->arch.hvm_domain.params[HVM_PARAM_PAE_ENABLED] )
#endif
- clear_bit(X86_FEATURE_NX & 31, edx);
+ __clear_bit(X86_FEATURE_NX & 31, edx);
#ifdef __i386__
/* Mask feature for Intel ia32e or AMD long mode. */
- clear_bit(X86_FEATURE_LAHF_LM & 31, ecx);
+ __clear_bit(X86_FEATURE_LAHF_LM & 31, ecx);
- clear_bit(X86_FEATURE_LM & 31, edx);
- clear_bit(X86_FEATURE_SYSCALL & 31, edx);
+ __clear_bit(X86_FEATURE_LM & 31, edx);
+ __clear_bit(X86_FEATURE_SYSCALL &...
2007 Aug 09
1
[PATCH] svm: allow guest to use EFER.FFXSE and EFER.LMSLE
...MMX extensions */
+#define X86_FEATURE_FFXSR (1*32+25) /* FFXSR instruction optimizations */
#define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */
#define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */
#define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */
@@ -93,7 +94,6 @@
#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */
#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */
#define X86_FEATURE_SVME (6*32+ 2) /* Secure Virtual Machine */
-#define X86_FEATURE_FFXSR (6*32+25) /* FFXSR instruction optimizations */
#define cpu_has(c, bit)...