Displaying 10 results from an estimated 10 matches for "x86_cr4_fsgsbase".
2020 Aug 29
2
[PATCH v6 38/76] x86/head/64: Set CR4.FSGSBASE early
...ad_64.S
> @@ -153,6 +153,13 @@ SYM_CODE_START(secondary_startup_64)
> orl $X86_CR4_LA57, %ecx
> 1:
> #endif
> +
> + ALTERNATIVE "jmp .Lstartup_write_cr4", "", X86_FEATURE_FSGSBASE
> +
> + /* Early exception handling uses FSGSBASE on APs */
> + orl $X86_CR4_FSGSBASE, %ecx
How is this supposed to work?
Alternatives haven't run that early yet and that piece of code looks
like this:
ffffffff81000067: eb 06 jmp ffffffff8100006f <secondary_startup_64+0x1f>
ffffffff81000069: 81 c9 00 00 01 00 or $0x10000,%ecx
f...
2020 Aug 29
2
[PATCH v6 38/76] x86/head/64: Set CR4.FSGSBASE early
...ad_64.S
> @@ -153,6 +153,13 @@ SYM_CODE_START(secondary_startup_64)
> orl $X86_CR4_LA57, %ecx
> 1:
> #endif
> +
> + ALTERNATIVE "jmp .Lstartup_write_cr4", "", X86_FEATURE_FSGSBASE
> +
> + /* Early exception handling uses FSGSBASE on APs */
> + orl $X86_CR4_FSGSBASE, %ecx
How is this supposed to work?
Alternatives haven't run that early yet and that piece of code looks
like this:
ffffffff81000067: eb 06 jmp ffffffff8100006f <secondary_startup_64+0x1f>
ffffffff81000069: 81 c9 00 00 01 00 or $0x10000,%ecx
f...
2020 Aug 31
0
[PATCH v6 38/76] x86/head/64: Set CR4.FSGSBASE early
...DE_START(secondary_startup_64)
> > orl $X86_CR4_LA57, %ecx
> > 1:
> > #endif
> > +
> > + ALTERNATIVE "jmp .Lstartup_write_cr4", "", X86_FEATURE_FSGSBASE
> > +
> > + /* Early exception handling uses FSGSBASE on APs */
> > + orl $X86_CR4_FSGSBASE, %ecx
>
> How is this supposed to work?
>
> Alternatives haven't run that early yet and that piece of code looks
> like this:
>
> ffffffff81000067: eb 06 jmp ffffffff8100006f <secondary_startup_64+0x1f>
> ffffffff81000069: 81 c9...
2013 Oct 10
10
[PATCH 0/4] x86: XSA-67 follow-up
1: correct LDT checks
2: add address validity check to guest_map_l1e()
3: use {rd,wr}{fs,gs}base when available
4: check for canonical address before doing page walks
Signed-off-by: Jan Beulich <jbeulich@suse.com>
2013 Aug 23
2
[PATCH] Nested VMX: Allow to set CR4.OSXSAVE if guest has xsave feature
From: Yang Zhang <yang.z.zhang@Intel.com>
We exposed the xsave feature to guest, but we didn''t allow guest
to set CR4.OSXSAVE when guest running in nested mode. This will
cause win 7 guest fail to use XP mode. In this patch, we allow guest
to set CR4.OSXSAVE in nested mode when it has the xsave feature.
Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com>
---
2011 Nov 24
0
[PATCH 6/6] X86: implement PCID/INVPCID for hvm
...v)->arch.hvm_vcpu.guest_cr[4] & X86_CR4_PCIDE))
#define hvm_pae_enabled(v) \
(hvm_paging_enabled(v) && ((v)->arch.hvm_vcpu.guest_cr[4] & X86_CR4_PAE))
#define hvm_smep_enabled(v) \
@@ -334,6 +336,7 @@ static inline int hvm_do_pmu_interrupt(s
(cpu_has_fsgsbase ? X86_CR4_FSGSBASE : 0) | \
((nestedhvm_enabled((_v)->domain) && cpu_has_vmx)\
? X86_CR4_VMXE : 0) | \
+ (cpu_has_pcid ? X86_CR4_PCIDE : 0) | \
(xsave_enabled(_v) ? X86_CR4_OSXSAVE : 0))))
/* These exceptions must always be int...
2013 Sep 23
11
[PATCH v4 0/4] x86/HVM: miscellaneous improvements
The first and third patches are cleaned up versions of an earlier v3
submission by Yang.
1: Nested VMX: check VMX capability before read VMX related MSRs
2: VMX: clean up capability checks
3: Nested VMX: fix IA32_VMX_CR4_FIXED1 msr emulation
4: x86: make hvm_cpuid() tolerate NULL pointers
Signed-off-by: Jan Beulich <jbeulich@suse.com>
2020 Aug 24
0
[PATCH v6 38/76] x86/head/64: Set CR4.FSGSBASE early
...x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -153,6 +153,13 @@ SYM_CODE_START(secondary_startup_64)
orl $X86_CR4_LA57, %ecx
1:
#endif
+
+ ALTERNATIVE "jmp .Lstartup_write_cr4", "", X86_FEATURE_FSGSBASE
+
+ /* Early exception handling uses FSGSBASE on APs */
+ orl $X86_CR4_FSGSBASE, %ecx
+
+.Lstartup_write_cr4:
movq %rcx, %cr4
/* Setup early boot stage 4-/5-level pagetables. */
--
2.28.0
2020 Aug 24
96
[PATCH v6 00/76] x86: SEV-ES Guest Support
From: Joerg Roedel <jroedel at suse.de>
Hi,
here is the new version of the SEV-ES client enabling patch-set. It is
based on the latest tip/master branch and contains the necessary
changes. In particular those ar:
- Enabling CR4.FSGSBASE early on supported processors so that
early #VC exceptions on APs can be handled.
- Add another patch (patch 1) to fix a KVM frame-size build
2020 Jul 24
86
[PATCH v5 00/75] x86: SEV-ES Guest Support
From: Joerg Roedel <jroedel at suse.de>
Hi,
here is a rebased version of the latest SEV-ES patches. They are now
based on latest tip/master instead of upstream Linux and include the
necessary changes.
Changes to v4 are in particular:
- Moved early IDT setup code to idt.c, because the idt_descr
and the idt_table are now static
- This required to make stack protector work early (or