search for: writevector

Displaying 3 results from an estimated 3 matches for "writevector".

2018 Nov 17
2
Per-write cycle count with ReadAdvance - Do I really need that?
...o). I think I may > need this ReadAdvance feature to work with my ARCH. > > It is about the scheduler info which describes reading my ARCH's vector > register. There are different latencies since forwarding/bypass appears. I > give it as below example: > > def : WriteRes<WriteVector, [MyArchVALU]> { let Latency = 6; } > ... > def MyWriteAddVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; } > def MyWriteMulVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; } > ... > > Here I defined 3 different Writes with same latency number. Be...
2018 Nov 19
2
Per-write cycle count with ReadAdvance - Do I really need that?
...n the register reader and > writer. I am freshman into tblgen. So I wonder if any other Target already > has other way to describe that . > > > Does this work for you? > > // Forward from a vector op (normal, add, mul) to a non-store. > def : ReadAdvance<MyReadVector, 5, [WriteVector]>; > def : ReadAdvance<MyReadVector, 3, [MyWriteAddVector]>; > def : ReadAdvance<MyReadVector, 1, [MyWriteMulVector]>; > > A ReadAdvance is associated with a pair of write resource -> read > resource. You can specify as many variants of read/write resources as you &...
2018 Nov 15
2
Per-write cycle count with ReadAdvance - Do I really need that?
...low thread (written in 3 years ago). I think I may need this ReadAdvance feature to work with my ARCH. It is about the scheduler info which describes reading my ARCH's vector register. There are different latencies since forwarding/bypass appears. I give it as below example: def : WriteRes<WriteVector, [MyArchVALU]> { let Latency = 6; } ... def MyWriteAddVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; } def MyWriteMulVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; } ... Here I defined 3 different Writes with same latency number. Below shows the forwarding. de...