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writesmemory
2012 Feb 23
2
[LLVMdev] [RFC] Remat Enhancements
I have a set of changes that enhances rematerialization to handle more
kinds of loads, specifically loads with multiple address registers.
This is a big win for some codes on x86.
I plan to send these up ASAP but I want to solicit a bit of guidance
first.
The change requires that live interval analysis be able to determine
whether and instruction is a load and whether an instruction writes to