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...o use SchedMachineModel: // ===---------------------------------------------------------------------===// // The following definitions describe the simpler per-operand machine model. // This works with MachineScheduler and will eventually replace itineraries. class A9WriteLMOpsListType<list<WriteSequence> writes> { list <WriteSequence> Writes = writes; SchedMachineModel SchedModel = ?; } // Cortex-A9 machine model for scheduling and other instruction cost heuristics. def CortexA9Model : SchedMachineModel { let IssueWidth = 2; // 2 micro-ops are dispatched per cycle. let Mic...

So if I use the SchedMachineModel method, can I just skip itineraries? Phil On Wed, Apr 20, 2016 at 12:29 PM, Sergei Larin <slarin at codeaurora.org> wrote: > Target does make a difference. VLIW needs more hand-holding. For what you > are describing it should be fairly simple. > > > > Best strategy – see what other targets do. ARM might be a good start for > generic

Hi Andrew, I seem to be making good progress on the P5600 scheduler using the new machine model but I've got a few questions about it. How would you represent an instruction that splits into two micro-ops and is dispatched to two different reservation stations? For example, I have two reservation stations (AGQ and FPQ). An FPU load instruction is split into a load micro-op which is

...e, if target has IF ID EX WB stages should I do: let BufferSize=0 in { def IF: ProcResource<1>; def ID: ProcResource<1>; def EX: ProcResource<1>; def WB: ProcResource<1>; } def : WriteRes<WriteALU, [IF, ID, EX1, WB]> ; or define each stage as SchedWrite type and use WriteSequence to define this sequence? Thanks, Kuan-Hsu 2013/10/16 Andrew Trick <atrick at apple.com> > > On Oct 15, 2013, at 9:28 PM, Zakk <zakk0610 at gmail.com> wrote: > > Hi Andy, thanks for your help!! > The scheduled code by method A is same as B when using the new machine...

...der processor) because it prevents FPLoad + FPx from being scheduled in the same cycle and fails to detect a conflict on FP ops 5 scheduled cycles ahead. A better way to express it would be: def P5600LD <[P5600UnitAGQ]> { let Latency = 4; } def P5600FP <[P5600UnitFP]>; def P5600FLD : WriteSequence<[P5600LD, P5600FP]>; Unfortunately, the implementation currently aggregates the processor resources, ignoring the fact that they are used on different cycles. This is totally fixable [2]. However, I don't know why you would care, since an out-of-order processor doing its job will mak...

On Oct 15, 2013, at 9:28 PM, Zakk <zakk0610 at gmail.com> wrote: > Hi Andy, thanks for your help!! > The scheduled code by method A is same as B when using the new machine model. > it's make sense, but there is the another problem, the scheduled code is badly. > > load/store instruction always reuse the same register I filed PR17593 with this information. However, I

Hi Andy, thanks for your help!! The scheduled code by method A is same as B when using the new machine model. it's make sense, but there is the another problem, the scheduled code is badly. load/store instruction always reuse the same register Source: #define N 2000000 static double b[N], c[N]; void Scale () { double scalar = 3.0; for (int j=0;j<N;j++) b[j] =