Displaying 6 results from an estimated 6 matches for "writeresources".
Did you mean:
writeresourceid
2014 Feb 18
2
[LLVMdev] Question about per-operand machine model
...source conflicts per cycle. In order to support this with LLVM, I expected a per-operand list of resources like latencies with a scheduling class.
Can I ask you something to modify on tablegen? I think that the 'WriteResourceID' field of 'MCWriteLatencyEntry' is for identifying the WriteResources of each defintion as commented on code. As you know, tablegen sets the 'WriteResourceID' field of 'MCWriteLatencyEntry' with 'WriteID' when the 'Write' of defition is referenced by a 'ReadAdvance'. If we always set this field with 'WriteID', it causes...
2014 Feb 19
2
[LLVMdev] Question about per-operand machine model
...t; this with LLVM, I expected a per-operand list of resources like
>> latencies with a scheduling class.
>>
>> Can I ask you something to modify on tablegen? I think that the
>> 'WriteResourceID' field of 'MCWriteLatencyEntry' is for identifying
>> the WriteResources of each defintion as commented on code. As you
>> know, tablegen sets the 'WriteResourceID' field of
>> 'MCWriteLatencyEntry' with 'WriteID' when the 'Write' of defition is
>> referenced by a 'ReadAdvance'. If we always set this field with
&...
2014 Feb 28
2
[LLVMdev] Question about per-operand machine model
...and list of resources like
>>>> latencies with a scheduling class.
>>>>
>>>> Can I ask you something to modify on tablegen? I think that the
>>>> 'WriteResourceID' field of 'MCWriteLatencyEntry' is for identifying
>>>> the WriteResources of each defintion as commented on code. As you
>>>> know, tablegen sets the 'WriteResourceID' field of
>>>> 'MCWriteLatencyEntry' with 'WriteID' when the 'Write' of defition is
>>>> referenced by a 'ReadAdvance'. If we alwa...
2014 Feb 18
2
[LLVMdev] Question about per-operand machine model
Hi Andy and all,
I have a question about per-operand machine model. I am finding some
relations between 'MCWriteLatencyEntry' and 'MCWriteProcResEntry'.
For example,
class InstTEST<..., InstrItinClass itin> : Instruction {
let Itinerary = Itin;
}
// I assume this MI writes 2 registers.
def TESTINST : InstTEST<..., II_TEST>
// schedule info
II_TEST:
2014 Mar 03
2
[LLVMdev] Question about per-operand machine model
...gt;>> latencies with a scheduling class.
>>>>>>
>>>>>> Can I ask you something to modify on tablegen? I think that the
>>>>>> 'WriteResourceID' field of 'MCWriteLatencyEntry' is for identifying
>>>>>> the WriteResources of each defintion as commented on code. As you
>>>>>> know, tablegen sets the 'WriteResourceID' field of
>>>>>> 'MCWriteLatencyEntry' with 'WriteID' when the 'Write' of defition is
>>>>>> referenced by a 'Read...
2014 Mar 04
2
[LLVMdev] Question about per-operand machine model
...eduling class.
>>>>>>>>
>>>>>>>> Can I ask you something to modify on tablegen? I think that the
>>>>>>>> 'WriteResourceID' field of 'MCWriteLatencyEntry' is for identifying
>>>>>>>> the WriteResources of each defintion as commented on code. As you
>>>>>>>> know, tablegen sets the 'WriteResourceID' field of
>>>>>>>> 'MCWriteLatencyEntry' with 'WriteID' when the 'Write' of defition is
>>>>>>>> r...