Displaying 6 results from an estimated 6 matches for "writeload".
2018 Mar 18
0
Generating a custom opcode from an LLVM intrinsic
Here's a couple examples for mapping an intrinsic to an X86 instruction
from X86InstrInfo.td. If you look for int_x86_* in any X86Instr*.td you can
find others.
let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in
def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
"clflushopt\t$src", [(int_x86_clflushopt addr:$src)],
IIC_SSE_PREFETCH>, PD;
let Predicates = [HasCLWB], SchedRW = [WriteLoad] in
def CLWB : I<0xAE, MRM6m, (outs), (ins i8me...
2018 Mar 19
4
Generating a custom opcode from an LLVM intrinsic
...7:43 PM, Craig Topper <craig.topper at gmail.com>
wrote:
> Here's a couple examples for mapping an intrinsic to an X86 instruction
> from X86InstrInfo.td. If you look for int_x86_* in any X86Instr*.td you can
> find others.
>
> let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in
> def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
> "clflushopt\t$src", [(int_x86_clflushopt addr:$src)],
> IIC_SSE_PREFETCH>, PD;
>
> let Predicates = [HasCLWB], SchedRW = [WriteLoad] in
> def CLWB : I<0...
2018 Mar 18
2
Generating a custom opcode from an LLVM intrinsic
Hello all. LLVM newbie here. If anything seems glaringly wrong with my use
of LLVM, that's probably why.
Here's what I'm trying to do. I have modified the gem5 simulator to accept
a "new" x86 instruction. I've done this by just reserving the opcode in
gem5's ISA specification, just as all other instructions are specified.
I'm trying to get an LLVM backend to
2018 Mar 19
0
Generating a custom opcode from an LLVM intrinsic
...aig.topper at gmail.com>
> wrote:
>
>> Here's a couple examples for mapping an intrinsic to an X86 instruction
>> from X86InstrInfo.td. If you look for int_x86_* in any X86Instr*.td you can
>> find others.
>>
>> let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in
>> def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
>> "clflushopt\t$src", [(int_x86_clflushopt addr:$src)],
>> IIC_SSE_PREFETCH>, PD;
>>
>> let Predicates = [HasCLWB], SchedRW = [WriteLoad] in
>>...
2014 Apr 16
2
[LLVMdev] X86 mmx movq disassembler fail
0x0f 0x6f 0xc8
And
0x0f 0x7f 0xc1
Should both be movq % mm0, % mm1. (AT&T)
However, llvm 3.4 at least does not recognise the second variant as being a
valid instruction.
We are currently compiling up latest src incase it has been fixed. If not,
could someone take a look or recommend how to fix?
Lee
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2018 Mar 20
1
Generating a custom opcode from an LLVM intrinsic
...>> wrote:
>>
>>> Here's a couple examples for mapping an intrinsic to an X86 instruction
>>> from X86InstrInfo.td. If you look for int_x86_* in any X86Instr*.td you can
>>> find others.
>>>
>>> let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in
>>> def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
>>> "clflushopt\t$src", [(int_x86_clflushopt addr:$src)],
>>> IIC_SSE_PREFETCH>, PD;
>>>
>>> let Predicates = [HasCLWB], SchedRW = [Wr...