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...ing predicates into code that work on MCInst too. A more complicated example involving TII method calls. ------------------------------------------------------ This code is taken from the AArch64 Cyclone scheduling model: ``` def WriteZPred : SchedPredicate<[{TII->isGPRZero(*MI)}]>; def WriteImmZ : SchedWriteVariant<[ SchedVar<WriteZPred, [WriteX]>, SchedVar<NoSchedPred, [WriteImm]>]>; ``` Predicate WriteZPred is used to check if a GPR instruction is a zero-idiom. The rationale is that zero-idioms have zero latency and don't con...

...nce to be a list of int and 2) changing tablegen to allow multiple (Proc)ReadAdvance records with the same read resource. The former solution doesn't seem ideal as it requires repeating the cycle count many times for targets that use long SchedWriteRes lists: -def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI, +def: ReadAdvance<ReadIM, [1, 1, 1, 1, 1, 1, 1, 1], [WriteImm, WriteI, WriteISReg, WriteIEReg,WriteIS, WriteID32,WriteID64, WriteIM32,WriteIM64]>; The latter is a bit more verbose when per...

...2) changing tablegen to allow > multiple (Proc)ReadAdvance records with the same read resource. > > The former solution doesn't seem ideal as it requires repeating the > cycle count many times for targets that use long SchedWriteRes lists: > > -def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI, > +def: ReadAdvance<ReadIM, [1, 1, 1, 1, 1, 1, 1, 1], [WriteImm, WriteI, > WriteISReg, WriteIEReg,WriteIS, > WriteID32,WriteID64, > WriteIM32,WriteIM64]>; > > The latter i...

...allow >> multiple (Proc)ReadAdvance records with the same read resource. >> >> The former solution doesn't seem ideal as it requires repeating the >> cycle count many times for targets that use long SchedWriteRes lists: >> >> -def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI, >> +def: ReadAdvance<ReadIM, [1, 1, 1, 1, 1, 1, 1, 1], [WriteImm, WriteI, >> WriteISReg, WriteIEReg,WriteIS, >> WriteID32,WriteID64, >> WriteIM32,WriteIM64]>; >&g...

Hello LLVM Developers, We are working on extending currently available register rematerialization to include cases where sequence of multiple instructions is required to rematerialize a value. We had a discussion on this in community mailing list and link is here: http://lists.llvm.org/pipermail/llvm-dev/2016-September/subject.html#104777 >From the above discussion and studying the code we