Displaying 2 results from an estimated 2 matches for "writefadd".
Did you mean:
write_adv
2014 Dec 26
2
[LLVMdev] X86 disassembler & assembler mismatch
...OpndItins itins = SSE_ALU_F32P> {
> def rri : PIi8<0xC2, MRMSrcReg,
> (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
> [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
> itins.rr, d>,
> Sched<[WriteFAdd]>;
> def rmi : PIi8<0xC2, MRMSrcMem,
> (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
> [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
> itins.rm, d>,
> Sched<[WriteFAddLd, ReadAfterLd]>;...
2014 Dec 26
2
[LLVMdev] X86 disassembler & assembler mismatch
hi,
some instructions mismatch between assembler & disassembler, like below.
it seems this happens with all SSECC related instructions?
thanks,
Jun
$ echo "cmpps xmm1, xmm2, 23" | ./Release+Asserts/bin/llvm-mc -assemble
-triple=x86_64 --output-asm-variant=1 -x86-asm-syntax=intel -show-encoding
.text
cmpps xmm1, xmm2, 23 # encoding: [0x0f,0xc2,0xca,0x17]
$