Displaying 1 result from an estimated 1 matches for "writebranch".
2015 Oct 15
3
what can cause a "CPU table is not sorted" assertion
...chedMachineModel {
// HW can decode 2 instructions per cycle.
let IssueWidth = 2;
let LoadLatency = 4;
let MispredictPenalty = 16;
// This flag is set to allow the scheduler to assign a default model to
// unrecognized opcodes.
let CompleteModel = 0;
}
def WriteALU : SchedWrite;
def WriteBranch : SchedWrite;
let SchedModel = MyTargetModel in {
// SLOT0 can handles everything
def Slot0 : ProcResource<1>;
// SLOT1 can't handles branches
def Slot1 : ProcResource<1>;
// Many micro-ops are capable of issuing on multiple ports.
def SlotAny : ProcResGroup<[Slot0, Slot1]>...