search for: write_ghcb_msr

...> + +#include "misc.h" + +static inline u64 read_ghcb_msr(void) +{ + unsigned long low, high; + + asm volatile("rdmsr\n" : "=a" (low), "=d" (high) : + "c" (MSR_AMD64_SEV_ES_GHCB)); + + return ((high << 32) | low); +} + +static inline void write_ghcb_msr(u64 val) +{ + u32 low, high; + + low = val & 0xffffffffUL; + high = val >> 32; + + asm volatile("wrmsr\n" : : "c" (MSR_AMD64_SEV_ES_GHCB), + "a"(low), "d" (high) : "memory"); +} + +#undef __init +#define __init + +/* Include code for ea...

...<asm/msr-index.h> #include <asm/ptrace.h> #include <asm/svm.h> #include "misc.h" +struct ghcb boot_ghcb_page __aligned(PAGE_SIZE); +struct ghcb *boot_ghcb; + static inline u64 read_ghcb_msr(void) { unsigned long low, high; @@ -35,8 +39,95 @@ static inline void write_ghcb_msr(u64 val) "a"(low), "d" (high) : "memory"); } +static enum es_result es_fetch_insn_byte(struct es_em_ctxt *ctxt, + unsigned int offset, + char *buffer) +{ + char *rip = (char *)ctxt->regs->ip; + + buffer[offset] = rip[offset]; + + return ES_OK; +}...

...t; #include <asm/svm.h> > > #include "misc.h" > > +struct ghcb boot_ghcb_page __aligned(PAGE_SIZE); > +struct ghcb *boot_ghcb; > + > static inline u64 read_ghcb_msr(void) > { > unsigned long low, high; > @@ -35,8 +39,95 @@ static inline void write_ghcb_msr(u64 val) > "a"(low), "d" (high) : "memory"); > } > > +static enum es_result es_fetch_insn_byte(struct es_em_ctxt *ctxt, > + unsigned int offset, > +...

...this_cpu_write(sev_es_in_nmi, true); +} + +void sev_es_nmi_complete(void) +{ + struct ghcb *ghcb; + + ghcb = this_cpu_ptr(&ghcb_page); + + ghcb_invalidate(ghcb); + ghcb_set_sw_exit_code(ghcb, SVM_VMGEXIT_NMI_COMPLETE); + ghcb_set_sw_exit_info_1(ghcb, 0); + ghcb_set_sw_exit_info_2(ghcb, 0); + + write_ghcb_msr(__pa(ghcb)); + VMGEXIT(); + + this_cpu_write(sev_es_in_nmi, false); +} + static u64 sev_es_get_jump_table_addr(void) { unsigned long flags; @@ -485,7 +508,10 @@ static enum es_result handle_vmmcall(struct ghcb *ghcb, static enum es_result handle_db_exception(struct ghcb *ghcb, struct e...

Hi, here is the first public post of the patch-set to enable Linux to run under SEV-ES enabled hypervisors. The code is mostly feature-complete, but there are still a couple of bugs to fix. Nevertheless, given the size of the patch-set, I think it is about time to ask for initial feedback of the changes that come with it. To better understand the code here is a quick explanation of SEV-ES first.

Hi, here is the first public post of the patch-set to enable Linux to run under SEV-ES enabled hypervisors. The code is mostly feature-complete, but there are still a couple of bugs to fix. Nevertheless, given the size of the patch-set, I think it is about time to ask for initial feedback of the changes that come with it. To better understand the code here is a quick explanation of SEV-ES first.

...; + unsigned long low, high; > + > + asm volatile("rdmsr\n" : "=a" (low), "=d" (high) : > + "c" (MSR_AMD64_SEV_ES_GHCB)); > + > + return ((high << 32) | low); > +} > + > +static inline void write_ghcb_msr(u64 val) > +{ > + u32 low, high; > + > + low = val & 0xffffffffUL; > + high = val >> 32; > + > + asm volatile("wrmsr\n" : : "c" (MSR_AMD64_SEV_ES_GHCB), > + "a"(low), "d" (high)...

...; + unsigned long low, high; > + > + asm volatile("rdmsr\n" : "=a" (low), "=d" (high) : > + "c" (MSR_AMD64_SEV_ES_GHCB)); > + > + return ((high << 32) | low); > +} > + > +static inline void write_ghcb_msr(u64 val) > +{ > + u32 low, high; > + > + low = val & 0xffffffffUL; > + high = val >> 32; > + > + asm volatile("wrmsr\n" : : "c" (MSR_AMD64_SEV_ES_GHCB), > + "a"(low), "d" (high)...