search for: write_control

...hat MMIO register accesses > by the same CPU thread to a particular device will arrive in program > order. > So it will arrive to the pci subsystem in program order, but the pci subsystem may reorder, right? I can just issue a read after the writes, something like: write_control read_control write op read op What do you think? > > + /* Clear the control register - clear the error code if previous control operation failed */ > > + snet_write_ctrl(regs, 0); > > + > > + /* Write opcode and VQ idx */ > > + val = opcode |...

depends on "autoconf: regenerate configure scripts with 4.4 version" This series removes some of the really old deadwood from the tools build and makes some other things which are on their way out configurable at build time with a default depending on how far down the slope I judge them to be. * nuke in tree copy of libaio * nuke obsolete tools: xsview, miniterm, lomount & sv *