search for: write8

...onmentName().equals("JIT")) { AsmStreamer.reset(createJITStreamer(*Context, *TAB, Out, MCE)); } else { AsmStreamer.reset(createMachOStreamer(*Context, *TAB, Out, MCE)); } What do you think ? Do you consider this to be acceptable ? Or just horrible ? - MCObjectWriter::Write8 and MCObjectWriter::WriteBytes are designed to write in a raw_ostream instance, to adapt them to the JIT, I see 2 possibilities : - Add a virtual keyword on Write8/WriteBytes and re-implement them in JITObjectWriter ? This is my current solution but I fear it's not so good for the performance...

I do have an opinion, but don't have enough time to comment in much depth. The approximate approach I had in mind sounds like what you describe, though, the JITObjectWriter is the core piece, the other pieces probably fall into place as it becomes obvious if they are needed. It should be pretty straightforward to bring up something which works for running code with no external symbols, if you

...CPU == "k6" || CPU == "k6-2" || CPU == "k6-3" || CPU == "geode" || + CPU == "winchip-c6" || CPU == "winchip2" || CPU == "c3" || + CPU == "c3-2") { for (uint64_t i = 0; i < Count; ++i) OW->Write8(0x90); return true;

...ontainer of offset/size that one can traverse generating each element in the correct endianess: // Pseudo code for (iterator it = begin(), ie = end(); it != ie; ++it) { switch (it.getValueSize()) { default: assert(0 && "Invalid size!"); case 1: OW->Write8 (uint8_t (it.getValue())); break; case 2: OW->Write16(uint16_t(it.getValue())); break; case 4: OW->Write32(uint32_t(it.getValue())); break; case 8: OW->Write64(uint64_t(it.getValue())); break; } } Note: ObjectWriter has a set of endian correcting routines as us...

...quot; || CPU == "k6-2" || CPU == "k6-3" || CPU == "geode" || > + CPU == "winchip-c6" || CPU == "winchip2" || CPU == "c3" || > + CPU == "c3-2") { > for (uint64_t i = 0; i < Count; ++i) > OW->Write8(0x90); > return true; > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

...traverse generating each element in the correct > endianess: > > // Pseudo code > for (iterator it = begin(), ie = end(); it != ie; ++it) { > switch (it.getValueSize()) { > default: > assert(0 && "Invalid size!"); > case 1: OW->Write8 (uint8_t (it.getValue())); break; > case 2: OW->Write16(uint16_t(it.getValue())); break; > case 4: OW->Write32(uint32_t(it.getValue())); break; > case 8: OW->Write64(uint64_t(it.getValue())); break; > } > } > > Note: ObjectWriter has a set o...

...averse generating each element in the correct > endianess: > > // Pseudo code > for (iterator it = begin(), ie = end(); it != ie; ++it) { > switch (it.getValueSize()) { > default: > assert(0 && "Invalid size!"); > case 1: OW->Write8 (uint8_t (it.getValue())); break; > case 2: OW->Write16(uint16_t(it.getValue())); break; > case 4: OW->Write32(uint32_t(it.getValue())); break; > case 8: OW->Write64(uint64_t(it.getValue())); break; > } > } > > Note: ObjectWriter has a set...

...ment in the correct >> endianess: >> >> // Pseudo code >> for (iterator it = begin(), ie = end(); it != ie; ++it) { >> switch (it.getValueSize()) { >> default: >> assert(0 && "Invalid size!"); >> case 1: OW->Write8 (uint8_t (it.getValue())); break; >> case 2: OW->Write16(uint16_t(it.getValue())); break; >> case 4: OW->Write32(uint32_t(it.getValue())); break; >> case 8: OW->Write64(uint64_t(it.getValue())); break; >> } >> } >> >> Note:...

This should allow testing when QEMU gets VIRTIO_PCI_CAP_PCI_CFG support, but I'm pretty sure we should never allow these patches upstream. Tested with lguest (in virtio-next), which supports VIRTIO_PCI_CAP_PCI_CFG. Rusty Russell (2): virtio_pci: abstract all MMIO accesses. virtio: Introducing virtio_pci.no_mmio, the worst boot option in history. drivers/virtio/virtio_pci_common.c |

This should allow testing when QEMU gets VIRTIO_PCI_CAP_PCI_CFG support, but I'm pretty sure we should never allow these patches upstream. Tested with lguest (in virtio-next), which supports VIRTIO_PCI_CAP_PCI_CFG. Rusty Russell (2): virtio_pci: abstract all MMIO accesses. virtio: Introducing virtio_pci.no_mmio, the worst boot option in history. drivers/virtio/virtio_pci_common.c |

...t;k6-2" || CPU == "k6-3" || CPU == "geode" || > > + CPU == "winchip-c6" || CPU == "winchip2" || CPU == "c3" || > > + CPU == "c3-2") { > > for (uint64_t i = 0; i < Count; ++i) > > OW->Write8(0x90); > > return true; > > _______________________________________________ > > LLVM Developers mailing list > > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >

Moving to LLVM dev to discuss the possibility of extending the cast infrastructure to handle this. On Tue, Nov 20, 2012 at 5:51 PM, John McCall <rjmccall at apple.com> wrote: > On Nov 18, 2012, at 5:05 PM, David Blaikie <dblaikie at gmail.com> wrote: >> TypeLoc casting looks bogus. >> >> TypeLoc derived types return true from classof when the dynamic type >>

...;(F); OW->WriteBytes(LF.getContents().str()); break; } case MCFragment::FT_Org: { - MCOrgFragment &OF = cast<MCOrgFragment>(F); + const MCOrgFragment &OF = cast<MCOrgFragment>(F); for (uint64_t i = 0, e = FragmentSize; i != e; ++i) OW->Write8(uint8_t(OF.getValue())); @@ -506,7 +506,7 @@ // Check that we aren't trying to write a non-zero contents (or fixups) // into a virtual section. This is to support clients which use standard // directives to fill the contents of virtual sections. - MCDataFragmen...

...} \ } while (0) -__EXTERN_INLINE unsigned int apecs_ioread8(void __iomem *xaddr) +__EXTERN_INLINE unsigned int apecs_ioread8(const void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; unsigned long result, base_and_type; @@ -420,7 +420,7 @@ __EXTERN_INLINE void apecs_iowrite8(u8 b, void __iomem *xaddr) *(vuip) ((addr << 5) + base_and_type) = w; } -__EXTERN_INLINE unsigned int apecs_ioread16(void __iomem *xaddr) +__EXTERN_INLINE unsigned int apecs_ioread16(const void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; unsigned long result, base_...

...} \ } while (0) -__EXTERN_INLINE unsigned int apecs_ioread8(void __iomem *xaddr) +__EXTERN_INLINE unsigned int apecs_ioread8(const void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; unsigned long result, base_and_type; @@ -420,7 +420,7 @@ __EXTERN_INLINE void apecs_iowrite8(u8 b, void __iomem *xaddr) *(vuip) ((addr << 5) + base_and_type) = w; } -__EXTERN_INLINE unsigned int apecs_ioread16(void __iomem *xaddr) +__EXTERN_INLINE unsigned int apecs_ioread16(const void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; unsigned long result, base_...

...} \ } while (0) -__EXTERN_INLINE unsigned int apecs_ioread8(void __iomem *xaddr) +__EXTERN_INLINE unsigned int apecs_ioread8(const void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; unsigned long result, base_and_type; @@ -420,7 +420,7 @@ __EXTERN_INLINE void apecs_iowrite8(u8 b, void __iomem *xaddr) *(vuip) ((addr << 5) + base_and_type) = w; } -__EXTERN_INLINE unsigned int apecs_ioread16(void __iomem *xaddr) +__EXTERN_INLINE unsigned int apecs_ioread16(const void __iomem *xaddr) { unsigned long addr = (unsigned long) xaddr; unsigned long result, base_...

Hi, Multiple architectures are affected in the first patch and all further patches depend on the first. Maybe this could go in through Andrew Morton's tree? Changes since v2 ================ 1. Drop all non-essential patches (cleanups), 2. Update also drivers/sh/clk/cpg.c . Changes since v1 ================ https://lore.kernel.org/lkml/1578415992-24054-1-git-send-email-krzk at

Hi, Changes since v1 ================ https://lore.kernel.org/lkml/1578415992-24054-1-git-send-email-krzk at kernel.org/ 1. Constify also ioreadX_rep() and mmio_insX(), 2. Squash lib+alpha+powerpc+parisc+sh into one patch for bisectability, 3. Add Geert's review, 4. Re-order patches so all optional driver changes are at the end. Description =========== The ioread8/16/32() and others have

Hi, Changes since v1 ================ https://lore.kernel.org/lkml/1578415992-24054-1-git-send-email-krzk at kernel.org/ 1. Constify also ioreadX_rep() and mmio_insX(), 2. Squash lib+alpha+powerpc+parisc+sh into one patch for bisectability, 3. Add acks and reviews, 4. Re-order patches so all optional driver changes are at the end. Description =========== The ioread8/16/32() and others have

Hi, Changes since v1 ================ https://lore.kernel.org/lkml/1578415992-24054-1-git-send-email-krzk at kernel.org/ 1. Constify also ioreadX_rep() and mmio_insX(), 2. Squash lib+alpha+powerpc+parisc+sh into one patch for bisectability, 3. Add acks and reviews, 4. Re-order patches so all optional driver changes are at the end. Description =========== The ioread8/16/32() and others have