search for: write32

...ail): 220.926392 read32 #3 +0x00100e10 -> 0x00070000 220.926406 read32 #3 +0x00100e14 -> 0x00010000 carveout_base = 0x70000000 carveout_size = 0x10000000 -- snip -- 223.300495 read32 #3 +0x00100c14 -> 0x00000000 223.300521 read32 #3 +0x00100c18 -> 0x00000000 223.300547 write32 #3 +0x00100c18 <- 0x000027ff base = (0x70000000 + 0x10000000) - ((0x27ff + 1) << 5) base = 0x7ffb0000 << in carveout 223.300573 read32 #3 +0x00100c14 -> 0x00000000 223.300599 write32 #3 +0x00100c14 <- 0x00000001 223.300625 read32 #3 +0x00100c1c -> 0x00000002 223.30...

Signed-off-by: Pierre Moreau <pierre.morrow at free.fr> --- drm/nouveau_drm.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drm/nouveau_drm.c b/drm/nouveau_drm.c index afb93bb..ffa1e4f 100644 --- a/drm/nouveau_drm.c +++ b/drm/nouveau_drm.c @@ -61,9 +61,10 @@ MODULE_PARM_DESC(debug, "debug string to pass to driver core"); static char

Updated set of patches for coverage. Changes: - change copyright lines - use gcov: instead of cover: in commit comment - use #ifdef in xen/common/sysctl.c instead of dummy inline function - added base documentation in docs/misc - added -h option to xencov

...ator it = begin(), ie = end(); it != ie; ++it) { switch (it.getValueSize()) { default: assert(0 && "Invalid size!"); case 1: OW->Write8 (uint8_t (it.getValue())); break; case 2: OW->Write16(uint16_t(it.getValue())); break; case 4: OW->Write32(uint32_t(it.getValue())); break; case 8: OW->Write64(uint64_t(it.getValue())); break; } } Note: ObjectWriter has a set of endian correcting routines as use above. The output routines like the snippet above would be in lib/MC/MCAssembler.cpp There is an MCInstFragment, but it d...

...; it != ie; ++it) { > switch (it.getValueSize()) { > default: > assert(0 && "Invalid size!"); > case 1: OW->Write8 (uint8_t (it.getValue())); break; > case 2: OW->Write16(uint16_t(it.getValue())); break; > case 4: OW->Write32(uint32_t(it.getValue())); break; > case 8: OW->Write64(uint64_t(it.getValue())); break; > } > } > > Note: ObjectWriter has a set of endian correcting routines as use above. > > The output routines like the snippet above would be in lib/MC/MCAssembler.cpp >...

...; it != ie; ++it) { > switch (it.getValueSize()) { > default: > assert(0 && "Invalid size!"); > case 1: OW->Write8 (uint8_t (it.getValue())); break; > case 2: OW->Write16(uint16_t(it.getValue())); break; > case 4: OW->Write32(uint32_t(it.getValue())); break; > case 8: OW->Write64(uint64_t(it.getValue())); break; > } > } > > Note: ObjectWriter has a set of endian correcting routines as use above. > > The output routines like the snippet above would be in lib/MC/MCAssembler.cpp &g...

...{ >> switch (it.getValueSize()) { >> default: >> assert(0 && "Invalid size!"); >> case 1: OW->Write8 (uint8_t (it.getValue())); break; >> case 2: OW->Write16(uint16_t(it.getValue())); break; >> case 4: OW->Write32(uint32_t(it.getValue())); break; >> case 8: OW->Write64(uint64_t(it.getValue())); break; >> } >> } >> >> Note: ObjectWriter has a set of endian correcting routines as use above. >> >> The output routines like the snippet above would be in...

...nstructions in a .o that it things are not part of the specific subflavor. This is where I noticed the problem originally. There are various comments to this effect but they are not totally accurate. // FIXME: get the real EABI Version from the Triple. void ARMELFObjectWriter::WriteEFlags() { Write32(ELF::EF_ARM_EABIMASK & DefaultEABIVersion); } The Triple is in general not enough. Any ideas no how to fix this? I have some but it will touch several architectures.

...1] << 8; - _v |= _p[2] << 16; - _v |= _p[3] << 24; + uint32_t _v; + + _v = ((const uint8_t *)_p)[0]; + _v |= ((const uint8_t *)_p)[1] << 8; + _v |= ((const uint8_t *)_p)[2] << 16; + _v |= ((const uint8_t *)_p)[3] << 24; return _v; } static inline void write32(le32_t *_p, uint32_t _v) { - _p[0] = _v & 0xFF; - _p[1] = (_v >> 8) & 0xFF; - _p[2] = (_v >> 16) & 0xFF; - _p[3] = (_v >> 24) & 0xFF; + ((uint8_t *)_p)[0] = _v & 0xFF; + ((uint8_t *)_p)[1] = (_v >> 8) & 0xFF; + ((uint8_t *)_p)[2] = (_v >>...

http://defect.opensolaris.org/bz/show_bug.cgi?id=1986 Summary: ''zfs destroy'' hangs on encrypted dataset Classification: Development Product: zfs-crypto Version: unspecified Platform: Other OS/Version: Solaris Status: NEW Severity: major Priority: P2 Component: other

This should allow testing when QEMU gets VIRTIO_PCI_CAP_PCI_CFG support, but I'm pretty sure we should never allow these patches upstream. Tested with lguest (in virtio-next), which supports VIRTIO_PCI_CAP_PCI_CFG. Rusty Russell (2): virtio_pci: abstract all MMIO accesses. virtio: Introducing virtio_pci.no_mmio, the worst boot option in history. drivers/virtio/virtio_pci_common.c |

This should allow testing when QEMU gets VIRTIO_PCI_CAP_PCI_CFG support, but I'm pretty sure we should never allow these patches upstream. Tested with lguest (in virtio-next), which supports VIRTIO_PCI_CAP_PCI_CFG. Rusty Russell (2): virtio_pci: abstract all MMIO accesses. virtio: Introducing virtio_pci.no_mmio, the worst boot option in history. drivers/virtio/virtio_pci_common.c |

Changes: - patch v2: - Adapt patch to work post KPTI and compiler changes - Redo all performance testing with latest configs and compilers - Simplify mov macro on PIE (MOVABS now) - Reduce GOT footprint - patch v1: - Simplify ftrace implementation. - Use gcc mstack-protector-guard-reg=%gs with PIE when possible. - rfc v3: - Use --emit-relocs instead of -pie to reduce

Changes: - patch v2: - Adapt patch to work post KPTI and compiler changes - Redo all performance testing with latest configs and compilers - Simplify mov macro on PIE (MOVABS now) - Reduce GOT footprint - patch v1: - Simplify ftrace implementation. - Use gcc mstack-protector-guard-reg=%gs with PIE when possible. - rfc v3: - Use --emit-relocs instead of -pie to reduce

These patches make the changes necessary to build the kernel as Position Independent Executable (PIE) on x86_64. A PIE kernel can be relocated below the top 2G of the virtual address space. It allows to optionally extend the KASLR randomization range from 1G to 3G. Thanks a lot to Ard Biesheuvel & Kees Cook on their feedback on compiler changes, PIE support and KASLR in general. Thanks to

These patches make the changes necessary to build the kernel as Position Independent Executable (PIE) on x86_64. A PIE kernel can be relocated below the top 2G of the virtual address space. It allows to optionally extend the KASLR randomization range from 1G to 3G. Thanks a lot to Ard Biesheuvel & Kees Cook on their feedback on compiler changes, PIE support and KASLR in general. Thanks to

Changes: - patch v3: - Update on message to describe longer term PIE goal. - Minor change on ftrace if condition. - Changed code using xchgq. - patch v2: - Adapt patch to work post KPTI and compiler changes - Redo all performance testing with latest configs and compilers - Simplify mov macro on PIE (MOVABS now) - Reduce GOT footprint - patch v1: - Simplify ftrace

Changes: - patch v1: - Simplify ftrace implementation. - Use gcc mstack-protector-guard-reg=%gs with PIE when possible. - rfc v3: - Use --emit-relocs instead of -pie to reduce dynamic relocation space on mapped memory. It also simplifies the relocation process. - Move the start the module section next to the kernel. Remove the need for -mcmodel=large on modules. Extends

Changes: - patch v1: - Simplify ftrace implementation. - Use gcc mstack-protector-guard-reg=%gs with PIE when possible. - rfc v3: - Use --emit-relocs instead of -pie to reduce dynamic relocation space on mapped memory. It also simplifies the relocation process. - Move the start the module section next to the kernel. Remove the need for -mcmodel=large on modules. Extends