search for: write1

...Not what I want. If someone can give me a hint, I would really appreciate it. Thank you. If I do this, reader1 can see the files (good), cannot create files (good), but can modify (write) existing files (bad!) ------- smb.conf ------- [native6-stuff] path = /native6-stuff valid users = write1 write2 write3 reader1 guest ok = no read-list = reader1 write-list write1 write2 write3 force group = writers public = no writable = yes printable = no create mask = 0664 directory mask = 0664 ----------- /etc/group ------------ writers:x:598:write1,write2,write3 -------...

Hi, I want a function to write some of its output into a text file with the following format: 'some text' output matrix A 'some more text' output matrix B 'some other text still' output matrix C ... The dimensions of matrices A, B, ... are different and the total number of matrices that I want to place in the text file depends on what I pass to the function. (I

Hi, I have been able to generate association rules for Market Basket Analysis using the following codes: **************************************************************************** ******************************************* library("arules") rules <- read.csv("write1.csv",na.strings=c(".", "NA", "", "?"),header=TRUE) transactions <- as(split(rules$Item, rules$ID), "transactions") getrules <- apriori(transactions, parameter = list(support=0.100, confidence=0.100)) summary(getrules) inspect(SO...

It does not work. I have tried to use the latest master today. But tblgen still give me information like error: Resources are defined for both SchedRead and its alias on processor MyArchModel def : ReadAdvance<MyReadVector, 3, [MyWriteAddVector]>; ^ Unless I change "MyReadVector" to another read like "MyReadVector1", it would not work. Debugging into tblgen, there is

...the pipeline stages here, not the operand latency list). Let's say you want to treat each stage of a pipeline as a separate type of unit: stage0: Decode stage1: Exec stage2: Write [InstrStage<1, [Decode0, Decode1], 0>, InstrStage<1, [Exec0, Exec1], 0>, InstrStage<1, [Write0, Write1, 0]>] Now when the first instruction is scheduled, it fills in the current row of the reservation table with Decode0, Exec0, Write0. This is counterintuitive because the instruction does not execute on all units in the same cycle, but it results in a more compact reservation table and still suf...